Abstract: Techniques for authentication of digital recordings are provided. An element of encrypted data is output in a recording environment. The element of encrypted data, embedded in a digital recording comprising at least one of audio data and image data captured in the recording environment, is extracted. A decrypted value is generated based on a private key and the first element of encrypted data, and the first decrypted value and a stored value associated with a first element of the digital recording are compared. The digital recording is authenticated based on the first decrypted value substantially matching the stored value.

Abstract: Described are techniques for presentation attack detection including a computer-implemented method of emitting a predetermined frequency pattern using at least one speaker communicatively coupled to a computer implementing a video-conference. The computer-implemented method further comprises collecting, by a camera communicatively coupled to the computer and overlapping with the emitting the predetermined frequency pattern, video data of a user engaged in the video-conference. The computer-implemented method further comprises determining that the video data is inconsistent with an expected response to the predetermined frequency pattern. The computer-implemented method further comprises generating an indication that the user engaged in the video-conference is performing a presentation attack.

Abstract: Aspects described herein include a computer-implemented method (and related system and computer program product) comprising receiving, from a bonding service, an authorization request for a predefined authorized use of a good or service by a user. The authorization request indicates that the user meets one or more predefined criteria for the predefined authorized use. The method further comprises determining one or more penalty conditions of a bonding agreement for the predefined authorized use by the user, and receiving, from the bonding service, a confirmation that the user agrees to meet the one or more penalty conditions of the bonding agreement. The method further comprises receiving, from an owner of the good or service, an authorization of the authorization request, and transmitting, responsive to authorization of the authorization request, a token to the bonding service that enables the user to access the predefined authorized use of the good or service.

Abstract: Aspects described herein include a computer-implemented method (and related system and computer program product) comprising receiving, from a bonding service, an authorization request for a predefined authorized use of a good or service by a user. The authorization request indicates that the user meets one or more predefined criteria for the predefined authorized use. The method further comprises determining one or more penalty conditions of a bonding agreement for the predefined authorized use by the user, and receiving, from the bonding service, a confirmation that the user agrees to meet the one or more penalty conditions of the bonding agreement. The method further comprises receiving, from an owner of the good or service, an authorization of the authorization request, and transmitting, responsive to authorization of the authorization request, a token to the bonding service that enables the user to access the predefined authorized use of the good or service.

Abstract: Techniques for analysis of verification parameters and reduction of training data are provided. A plurality of test results is received, where each of the plurality of test results specifies a respective one or more parameters and a respective one or more events. A list of parameters used to stimulate computing logic is determined. Additionally, a plurality of relevant parameters is generated, corresponding to parameters in the list of parameters that have at least two distinct values specified in the plurality of test results. A plurality of training cases is generated based on the plurality of test results and the plurality of relevant parameters. Further, a neural network is generated for design verification of the computing logic based on the plurality of relevant parameters. The neural network is trained based on the plurality of training cases.

Abstract: A computer system, processor, and method for processing information is disclosed that includes watching logical operations to detect unauthorized attempts to access a register, and taking evasive action in response to detecting unauthorized attempts to access the register. In an embodiment, the register is a hidden, secret, restricted, or undocumented register, and the method further includes, in response to unauthorized attempts to access the secret register, locking the contents of the secret register. The evasive action may include one or more of interrupting the operations of the processor; causing the processor to shut-down, malfunction, lock, self-destruct; no longer providing read or write permission or access to the register; releasing data disguised to look like the real register data while not releasing the real data; and combinations thereof.

Abstract: Techniques for enhanced security for disconnected devices are provided. A request for one or more attributes of a security component is received by the security component, from a requesting device. The one or more attributes are provided to the requesting device, where the requesting device transmits the one or more attributes to a network service, where the security component is not able to communicate with the network service. A token is received from the requesting device, where the requesting device received the token in response to transmitting the one or more attributes to the network service. A level of access is determined for the requesting device, based on validating the token using a predefined configuration of the security component. Finally, the determined level of access is provided to the requesting device.

Abstract: Techniques for authentication of digital recordings are provided. An element of encrypted data is output in a recording environment. The element of encrypted data, embedded in a digital recording comprising at least one of audio data and image data captured in the recording environment, is extracted. A decrypted value is generated based on a private key and the first element of encrypted data, and the first decrypted value and a stored value associated with a first element of the digital recording are compared. The digital recording is authenticated based on the first decrypted value substantially matching the stored value.

Abstract: Performing an operation comprising extracting a first element of encrypted data embedded in a digital recording comprising at least one of audio data and image data captured in a recording environment, generating a first decrypted value, the generating performed by execution of a cryptography algorithm based on a private key and the first element of encrypted data, comparing the first decrypted value and a stored value associated with a first element of the digital recording, and authenticating the digital recording based on the first decrypted value substantially matching the stored value.

Abstract: Techniques for enhanced security for disconnected devices are provided. A request for one or more attributes of a security component is received by the security component, from a requesting device. The one or more attributes are provided to the requesting device, where the requesting device transmits the one or more attributes to a network service, where the security component is not able to communicate with the network service. A token is received from the requesting device, where the requesting device received the token in response to transmitting the one or more attributes to the network service. A level of access is determined for the requesting device, based on validating the token using a predefined configuration of the security component. Finally, the determined level of access is provided to the requesting device.

Abstract: A computer system, processor, and method for processing information is disclosed that includes watching logical operations to detect unauthorized attempts to access a register, and taking evasive action in response to detecting unauthorized attempts to access the register. In an embodiment, the register is a hidden, secret, restricted, or undocumented register, and the method further includes, in response to unauthorized attempts to access the secret register, locking the contents of the secret register. The evasive action may include one or more of interrupting the operations of the processor; causing the processor to shut-down, malfunction, lock, self-destruct; no longer providing read or write permission or access to the register; releasing data disguised to look like the real register data while not releasing the real data; and combinations thereof.

Abstract: Techniques for analysis of verification parameters and reduction of training data are provided. A plurality of test results is received, where each of the plurality of test results specifies a respective one or more parameters and a respective one or more events. A list of parameters used to stimulate computing logic is determined. Additionally, a plurality of relevant parameters is generated, corresponding to parameters in the list of parameters that have at least two distinct values specified in the plurality of test results. A plurality of training cases is generated based on the plurality of test results and the plurality of relevant parameters. Further, a neural network is generated for design verification of the computing logic based on the plurality of relevant parameters. The neural network is trained based on the plurality of training cases.

Abstract: Performing an operation comprising extracting a first element of encrypted data embedded in a digital recording comprising at least one of audio data and image data captured in a recording environment, generating a first decrypted value, the generating performed by execution of a cryptography algorithm based on a private key and the first element of encrypted data, comparing the first decrypted value and a stored value associated with a first element of the digital recording, and authenticating the digital recording based on the first decrypted value substantially matching the stored value.

Abstract: A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input.

Abstract: A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input.

Abstract: A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input.

Abstract: In a particular embodiment, a method may include creating a plurality of variable depth instruction FIFOs and a plurality of data caches from a plurality of caches corresponding to a plurality of processors, where the plurality of caches and the plurality of processors correspond to MIMD architecture. The method may also include configuring the plurality of variable depth instruction FIFOs to implement SIMD architecture. The method may also include configuring the plurality of variable depth instruction FIFOs for at least one of SIMD operation, SIMD operation with staging, or RC-SIMD operation.

Abstract: A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input.