Abstract: A system for in-circuit testing of an electronic circuit device utilizes a distributed processing architecture wherein separate controllers are used to control the testing and for data collection and correlation of the collected data to the testing conditons. In a preferred embodiment, the testing is conducted by sending test vector addresses from the test controller to each of the driver/sensor boards in the testor electronics, which addresses, in turn, are used to access driver memories containing the test conditions corresponding to the test vector addresses. In the method of the present invention, the circuit containing the device is powered up and a tester coupling mechanism is connected to the terminals of the device. Determinations are made of the physical orientation of the device with respect to the tester coupling mechanism, and of whether the device terminals are in electrical contact with the tester mechanism and with the other components of the circuit.

Abstract: A processor controlled IC component test apparatus adapted to be employed in-line with automatic IC DIP component handling equipment is capable of conducting a preselected verification check of each IC device regardless of the orientation of the DIP in the device contact receptable of the IC handling apparatus. As each device under test (DUT) is inserted into the apparatus test head, a pin-check residual voltage measurement test is conducted to ensure that all the pins of the DUT are in contact with the contact terminals of the test head. If the pin-check test establishes that all the pins of the DUT are in contact with the contact terminals of the test head, a prescribed non-destructive impedance measurement test is carried out in order to determine the orientation of the DIP in the test head.