Abstract: Systems, methods and computer program products generally include a vector by vector subtraction method per wafer. A first layer is exposed to form a pattern image on a wafer and the overlay data of alignment registration marks at multiple locations relative to alignment registration marks of a baseline reference are measured. The first layer is then reworked and exposed to form the same pattern image and the overlay data of alignment registration marks at multiple locations relative to alignment registration marks of a first layer are measured. The overlay data of the reworked first layer is subtracted from the overlay data of the first layer to provide an overlay difference at each of the multiple locations. The overlay difference is converted to a pre-correction factor of a magnitude opposite that of the overlay difference and is applied to exposure of a second layer provided on the first layer.

Abstract: Systems, methods and computer program products generally include a vector by vector subtraction method per wafer. A first layer is exposed to form a pattern image on a wafer and the overlay data of alignment registration marks at multiple locations relative to alignment registration marks of a baseline reference are measured. The first layer is then reworked and exposed to form the same pattern image and the overlay data of alignment registration marks at multiple locations relative to alignment registration marks of a first layer are measured. The overlay data of the reworked first layer is subtracted from the overlay data of the first layer to provide an overlay difference at each of the multiple locations. The overlay difference is converted to a pre-correction factor of a magnitude opposite that of the overlay difference and is applied to exposure of a second layer provided on the first layer.

Abstract: A photomask lithography simulation model is created for making a semiconductor chip. Poor metrology is filtered and removed from a contour-specific metrology dataset to improve performance of the photomask. Filtering is performed by the application of a weighting scheme.

Abstract: A photomask lithography simulation model is created for making a semiconductor chip. Poor metrology is filtered and removed from a contour-specific metrology dataset to improve performance of the photomask. Filtering is performed by the application of a weighting scheme.

Abstract: A photomask lithography simulation model is created for making a semiconductor chip. Poor metrology is filtered and removed from a contour-specific metrology dataset to improve performance of the photomask. Filtering is performed by the application of a weighting scheme.

Abstract: A photomask lithography simulation model is created for making a semiconductor chip. Poor metrology is filtered and removed from a contour-specific metrology dataset to improve performance of the photomask. Filtering is performed by the application of a weighting scheme.

Abstract: Cut spacer reference marks, targets having such cut spacer reference marks, and methods of making the same by forming spacer gratings around grating lines on a first layer, and fabricating an angled template mask that extends across and resides at an angle with respect to such spacer gratings. Angled, cut spacer gratings are etched into a second layer using the angled template mask to superimpose at least a portion of the spacer gratings of the first layer into the second layer.

Abstract: Cut spacer reference marks, targets having such cut spacer reference marks, and methods of making the same by forming spacer gratings around grating lines on a first layer, and fabricating an angled template mask that extends across and resides at an angle with respect to such spacer gratings. Angled, cut spacer gratings are etched into a second layer using the angled template mask to superimpose at least a portion of the spacer gratings of the first layer into the second layer.

Abstract: Cut spacer reference marks, targets having such cut spacer reference marks, and methods of making the same by forming spacer gratings around grating lines on a first layer, and fabricating a template mask that extends across and perpendicular to such spacer gratings. Cut spacer gratings are etched into a second layer using the template mask to superimpose at least a portion of the spacer gratings of the first layer into the second layer.

Abstract: A method for forming a mask layout is described. A plurality of phase shapes are formed on either side of a critical feature of a design layout of an intergrated circuit chip having a plurality of critical features. A plurality of transition edges are identified from the edges of each phase shape. Each transition edge is parallel to critical feature. A transition space is identified as defined by one of the group including two transition edges and one transition edge. A transition polygon is formed by closing each transition space with at least one closing edge. Each transition polygon is transformed into a printing assist feature. A mask layout is formed from the printing assist features and critical features.

Abstract: A lithographic structure comprising: an organic antireflective material disposed on a substrate, and a silicon antireflective material disposed on the organic antireflective material. The silicon antireflective material comprises a crosslinked polymer with a SiOx backbone, a chromophore, and a transparent organic group that is substantially transparent to 193 nm or 157 nm radiation. In combination, the organic antireflective material and the silicon antireflective material provide an antireflective material suitable for deep ultraviolet lithography. The invention is also directed to a process of making the lithographic structure.

Abstract: A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements.

Abstract: A lithographic structure comprising: an organic antireflective material disposed on a substrate, and a silicon antireflective material disposed on the organic antireflective material. The silicon antireflective material comprises a crosslinked polymer with a SiOx backbone, a chromophore, and a transparent organic group that is substantially transparent to 193 nm or 157 nm radiation. In combination, the organic antireflective material and the silicon antireflective material provide an antireflective material suitable for deep ultraviolet lithography. The invention is also directed to a process of making the lithographic structure.

Abstract: A lithographic structure comprising: an organic antireflective material disposed on a substrate; and a silicon antireflective material disposed on the organic antireflective material. The silicon antireflective material comprises a crosslinked polymer with a SiOx backbone, a chromophore, and a transparent organic group that is substantially transparent to 193 nm or 157 nm radiation. In combination, the organic antireflective material and the silicon antireflective material provide an antireflective material suitable for deep ultraviolet lithography. The invention is also directed to a process of making the lithographic structure.

Abstract: A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements.

Abstract: An underlayer to be patterned with a composite pattern is formed on a substrate. The composite pattern is decomposed into a first pattern and a second pattern, each having reduced complexity than the composite pattern. A hard mask layer is formed directly on the underlying layer. A first photoresist is applied over the hard mask layer and lithographically patterned with the first pattern, which is transferred into the hard mask layer by a first etch. A second photoresist is applied over the hard mask layer. The second photoresist is patterned with the second pattern to expose portions of the underlying layer. The exposed portions of the underlying layer are etched employing the second photoresist and the hard mask layer, which contains the first pattern so that the composite pattern is transferred into the underlying layer.

Abstract: A method for mask layout formation including forming a plurality of phase shapes on either side of a critical feature of a design layout of an integrated circuit chip having a plurality of critical features, wherein each phase shape has an edge; identifying a plurality of transition edges from the edges, wherein each transition edge is parallel to a critical feature; identifying a transition space defined by one of a group including two transition edges, wherein the space is external to all phase shapes, and one transition edge, wherein the space is external to all phase shapes; forming a transition polygon by closing each transition space with at least one closing edge, wherein each closing edge is perpendicular to the plurality of transition edges; transforming each transition polygon into a printing assist feature; and forming a first mask layout or a second mask layout from the printing assist features and the critical features.

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features.

Abstract: Methods of forming line ends and a related memory cell including the line ends are disclosed. In one embodiment, the method includes forming a first device element and a second device element separated from the first device element by a space; and forming a first line extending from the first device element, the first line including a bulbous line end over the space and distanced from the first device element, and a second line extending from the second device element, the second line including a bulbous line end over the space and distanced from the second device element.

Abstract: A lithographic structure consisting essentially of: an organic antireflective material disposed on a substrate; a vapor-deposited RCHX material, wherein R is one or more elements selected from the group consisting of Si, Ge, B, Sn, Fe and Ti, and wherein X is not present or is one or more elements selected from the group consisting of O, N, S and F; and a photoresist material disposed on the RCHX material. The invention is also directed to methods of making the lithographic structure, and using the structure to pattern a substrate.