Patents by Inventor Scott D. Hanh

Scott D. Hanh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Machine check architecture execution environment for non-microcoded processor
    Patent number: 9141461
    Abstract: A technology for implementing a method for a machine check architecture environment. A method of the disclosure includes obtaining an occurrence of an error. The occurrence of the error causes a non-microcoded processing device to enter an error monitoring state. The method further processes the error using a dedicated memory portion for the error monitoring state while the non-microcoded processing device is in the error monitoring state. The error monitoring state is dedicated to error processing. The method further determines information associated with the error. The information associated with the error is in a predefined format.
    Type: Grant
    Filed: June 23, 2013
    Date of Patent: September 22, 2015
    Assignee: Intel Corporation
    Inventors: Willam C. Rash, Scott D. Hanh, Glenn J. Hinton
  • PROCESSORS HAVING HETEROGENEOUS CORES WITH DIFFERENT INSTRUCTIONS AND/OR ARCHITECURAL FEATURES THAT ARE PRESENTED TO SOFTWARE AS HOMOGENEOUS VIRTUAL CORES
    Publication number: 20150007196
    Abstract: A processor of an aspect includes a first heterogeneous physical compute element having a first set of supported instructions and architectural features, and a second heterogeneous physical compute element having a second set of supported instructions and architectural features. The second set of supported instructions and architectural features is different than the first set of supported instructions and architectural features. The processor also includes a workload and architectural state migration module coupled with the first and second heterogeneous physical compute elements. The workload and state migration module is operable to migrate a workload and associated architectural state from the first heterogeneous physical compute element to the second heterogeneous physical compute element in response to an attempt by the workload to perform at least one of an unsupported instruction and an unsupported architectural feature on the first heterogeneous physical compute element.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: BRET L. TOLL, Jason W. Brandt, Eliezer Weissmann, Inder M. Sodhi, David A. Koufaty, Scott D. Hanh
  • MACHINE CHECK ARCHITECTURE EXECUTION ENVIRONMENT FOR NON-MICROCODED PROCESSOR
    Publication number: 20140380085
    Abstract: A technology for implementing a method for a machine check architecture environment. A method of the disclosure includes obtaining an occurrence of an error. The occurrence of the error causes a non-microcoded processing device to enter an error monitoring state. The method further processes the error using a dedicated memory portion for the error monitoring state while the non-microcoded processing device is in the error monitoring state. The error monitoring state is dedicated to error processing. The method further determines information associated with the error. The information associated with the error is in a predefined format.
    Type: Application
    Filed: June 23, 2013
    Publication date: December 25, 2014
    Inventors: Willam C. Rash, Scott D. Hanh, Glenn J. Hinton