Abstract: Systems and methods are provided for detecting defects caused by cracks in an integrated circuit, which may arise during or after a silicon wafer is singulated into separate integrated circuits. An integrated circuit may include crack detection circuitry including a metal circuit. The metal circuit may fracture or break due to crack propagation through a portion of the integrated circuit. In the event of a crack, testing may detect the fracture of the metal circuit. The crack detection circuitry may also detect accurate operation of circuitry of the integrated circuit.

Abstract: A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respective layer of the first circuit and second circuit building blocks (i) a used portion and (ii) a free portion. The used portion corresponds to a functional portion of the respective circuit building block and the free portion corresponds to a non-functional portion of the respective circuit building block. The method further includes establishing packing keys with respect to the determined physical extent boundaries of each layer of the first circuit and second circuit building blocks, respectively. The packing keys define an interlocking characteristic for packing compaction of the corresponding first circuit or second circuit building block with another circuit building block.

Abstract: A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respective layer of the first circuit and second circuit building blocks (i) a used portion and (ii) a free portion. The used portion corresponds to a functional portion of the respective circuit building block and the free portion corresponds to a non-functional portion of the respective circuit building block. The method further includes establishing packing keys with respect to the determined physical extent boundaries of each layer of the first circuit and second circuit building blocks, respectively. The packing keys define an interlocking characteristic for packing compaction of the corresponding first circuit or second circuit building block with another circuit building block.

Abstract: An EUV mask (10, 309) includes an opening (26) that helps to attenuate and phase shift extreme ultraviolet radiation using a subtractive rather than additive method. A first embedded layer (20) and a second embedded layer (21) may be provided between a lower multilayer reflective stack (14) and an upper multilayer reflective stack (22) to ensure an appropriate and accurate depth of the opening (26), while allowing for defect inspection of the EUV mask (10, 309) and optional defect repair. An optional ARC layer (400) may be deposited in region (28) to reduce the amount of reflection within dark region (28). Alternately, a single embedded layer of hafnium oxide, zirconium oxide, tantalum silicon oxide, tantalum oxide, or the like, may be used in place of embedded layers (20, 21). Optimal thicknesses and locations of the various layers are described.

Abstract: Methods and apparatus are provided for extreme ultraviolet phase shift masks. The apparatus comprises a substrate, a reflectance region, and an attenuating phase shifter. The reflectance region overlies the substrate. The attenuating phase shifter overlies the reflectance region. The attenuating phase shifter includes a plurality of openings that expose portions of the reflectance region. The attenuating phase shifter attenuates radiation through a combination of absorption and destructive interference. The method comprises projecting radiation having a wavelength less than 40 nanometers towards a mask having a plurality of openings through an attenuating phase shifter. The plurality of openings expose a reflectance region in the mask. The attenuating phase shifter is less than 700 angstroms thick. Radiation impinging on the reflectance region exposed by said plurality of openings is reflected whereas radiation impinging on the attenuating phase shifter is attenuated and shifted in phase.

Abstract: An exemplary method for using multi-tiered templates with imprint lithography for producing dual damascene features is disclosed as comprising the steps of inter alia: positioning (step 150) a multi-tiered lithographic template (130) in contact with a resist layer (120); applying pressure to the template (130) so that the resist material (120) flows into the relief pattern of the template (130) thereby forming a patterned resist layer (125); optionally curing the patterned resist layer (125); removing (step 160) the template (130) from the patterned resist layer (125); and etching (steps 170, 180) the patterned resist layer (125) to develop a via-and-trench pattern in the patterning layer (117). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize the fabrication of dual damascene or other multi-tiered structures.

Abstract: A method for compensating for flare-induced critical dimensions (CD) changes in photolithography. Changes in the flare level results in undesirable CD changes. The method when used in extreme ultraviolet (EUV) lithography essentially eliminates the unwanted CD changes. The method is based on the recognition that the intrinsic level of flare for an EUV camera (the flare level for an isolated sub-resolution opaque dot in a bright field mask) is essentially constant over the image field. The method involves calculating the flare and its variation over the area of a patterned mask that will be imaged and then using mask biasing to largely eliminate the CD variations that the flare and its variations would otherwise cause. This method would be difficult to apply to optical or DUV lithography since the intrinsic flare for those lithographies is not constant over the image field.

Abstract: A desired pattern is formed in a photoresist layer that overlies a semiconductor wafer using a reflective mask. This mask is formed by consecutively depositing a reflective layer, an absorber layer and an anti-reflective (ARC) layer. The ARC layer is patterned according to the desired pattern. The ARC layer is inspected to find areas in which the desired pattern is not achieved. The ARC layer is then repaired to achieve the desired pattern with the absorber layer protecting the reflective layer. The desired pattern is transferred to the absorber layer to reveal the reflective portion of mask. Radiation is reflected off the reflective mask to the semiconductor wafer to expose the photoresist layer overlying the semiconductor wafer with the desired pattern.

Abstract: A desired pattern is formed in a photoresist layer that overlies a semiconductor wafer using a reflective mask. This mask is formed by consecutively depositing a reflective layer, an absorber layer and an anti-reflective (ARC) layer. The ARC layer is patterned according to the desired pattern. The ARC layer is inspected to find areas in which the desired pattern is not achieved. The ARC layer is then repaired to achieve the desired pattern with the absorber layer protecting the reflective layer. The desired pattern is transferred to the absorber layer to reveal the reflective portion of mask. Radiation is reflected off the reflective mask to the semiconductor wafer to expose the photoresist layer overlying the semiconductor wafer with the desired pattern.

Abstract: A removable pellicle for a lithographic mask that provides active and robust particle protection, and which utilizes a traditional pellicle and two deployments of thermophoretic protection to keep particles off the mask. The removable pellicle is removably attached via a retaining structure to the mask substrate by magnetic attraction with either contacting or non-contacting magnetic capture mechanisms. The pellicle retaining structural is composed of an anchor piece secured to the mask substrate and a frame member containing a pellicle. The anchor piece and the frame member are in removable contact or non-contact by the magnetic capture or latching mechanism. In one embodiment, the frame member is retained in a floating (non-contact) relation to the anchor piece by magnetic levitation. The frame member and the anchor piece are provided with thermophoretic fins which are interdigitated to prevent particles from reaching the patterned area of the mask.

Abstract: A process for creating a mask substrate involving depositing: 1) a coating on one or both sides of a low thermal expansion material EUVL mask substrate to improve defect inspection, surface finishing, and defect levels; and 2) a high dielectric coating, on the backside to facilitate electrostatic chucking and to correct for any bowing caused by the stress imbalance imparted by either other deposited coatings or the multilayer coating of the mask substrate. An film, such as TaSi, may be deposited on the front side and/or back of the low thermal expansion material before the material coating to balance the stress. The low thermal expansion material with a silicon overlayer and a silicon and/or other conductive underlayer enables improved defect inspection and stress balancing.

Abstract: A method of forming a lithographic mask, including exposing an energy beam on a first selected spot (118) on the patterning layer of a mask substrate, within a selected portion (117) on the patterning layer, and exposing an energy beam on a second selected spot (122) on the patterning layer. The selected portion corresponds to a lithographic feature (116) and has a boundary (128) including a plurality of boundary segments defining a polygon. The energy beam is exposed on the first selected spot (118) at a first dosage, and at the second selected spot (122) at a second dosage that does not equal the first dosage. According to the present invention, a lithographic feature (116) is provided on the lithographic mask and includes a serif (126), a portion of which is provided by altering the dosage level at the second selected spot.