Abstract: A capacitive sensing system based on projected self-capacitance is suitable for use in printing systems/products to sense paper tray status. In example embodiments, a capacitive sensing system is adapted for sensing the condition/characteristics of paper in the paper tray, such as paper size, stack height and page count and paper dielectric. The capacitive sensing system can be configured with one or more shielded capacitive sensors incorporated into the paper tray, and oriented relative to the paper according to the paper condition/characteristic sensed.

Abstract: A capacitive sensing system based on projected self-capacitance is suitable for use in printing systems/products to sense paper tray status. In example embodiments, a capacitive sensing system is adapted for sensing the condition/characteristics of paper in the paper tray, such as paper size, stack height and page count and paper dielectric. The capacitive sensing system can be configured with one or more shielded capacitive sensors incorporated into the paper tray, and oriented relative to the paper according to the paper condition/characteristic sensed.

Abstract: A circuit includes an analog-to-digital converter configured to receive an analog input signal and generate first digital values at a first sampling rate. The first digital values have a first bit-width. The circuit also includes an interpolator configured to receive the first digital values and generate second digital values at a second sampling rate higher than the first sampling rate. The second digital values have a second bit-width equal to or greater than the first bit-width. The circuit further includes a digital filter configured to receive the second digital values and perform bit-width reduction in a recoverable manner to generate third digital values. The third digital values have a third bit-width less than the first and second bit-widths. The circuit could optionally include a recovery circuit configured to process the third digital values to generate recovered digital values at the first sampling rate. The recovered digital values have the first bit-width.

Abstract: A circuit includes an analog-to-digital converter configured to receive an analog input signal and generate first digital values at a first sampling rate. The first digital values have a first bit-width. The circuit also includes an interpolator configured to receive the first digital values and generate second digital values at a second sampling rate higher than the first sampling rate. The second digital values have a second bit-width equal to or greater than the first bit-width. The circuit further includes a digital filter configured to receive the second digital values and perform bit-width reduction in a recoverable manner to generate third digital values. The third digital values have a third bit-width less than the first and second bit-widths. The circuit could optionally include a recovery circuit configured to process the third digital values to generate recovered digital values at the first sampling rate. The recovered digital values have the first bit-width.