Patents by Inventor Scott D. Luning
Scott D. Luning has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10186524Abstract: Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.Type: GrantFiled: March 5, 2018Date of Patent: January 22, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: David Pritchard, Lixia Lei, Deniz E. Civay, Scott D. Luning, Neha Nayyar
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Patent number: 10181522Abstract: Structures for a field-effect transistor and fabrication methods for forming a structure for a field-effect transistor. The structure may include a gate electrode, a source/drain region formed adjacent to a vertical sidewall of the gate electrode, and a conductive link that couples the vertical sidewall of the gate electrode with the source/drain region.Type: GrantFiled: February 21, 2017Date of Patent: January 15, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Tuhin Guha Neogi, Scott D. Luning, David Pritchard, Kasun Anupama Punchihewa
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Publication number: 20180240885Abstract: Structures for a field-effect transistor and fabrication methods for forming a structure for a field-effect transistor. The structure may include a gate electrode, a source/drain region formed adjacent to a vertical sidewall of the gate electrode, and a conductive link that couples the vertical sidewall of the gate electrode with the source/drain region.Type: ApplicationFiled: February 21, 2017Publication date: August 23, 2018Inventors: Tuhin Guha Neogi, Scott D. Luning, David Pritchard, Kasun Anupama Punchihewa
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Publication number: 20180197882Abstract: Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.Type: ApplicationFiled: March 5, 2018Publication date: July 12, 2018Inventors: David PRITCHARD, Lixia LEI, Deniz E. CIVAY, Scott D. LUNING, Neha NAYYAR
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Patent number: 9941301Abstract: Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.Type: GrantFiled: December 22, 2016Date of Patent: April 10, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: David Pritchard, Lixia Lei, Deniz E. Civay, Scott D. Luning, Neha Nayyar
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Patent number: 9373548Abstract: A CMOS circuit is provided that includes a PMOS transistor, an NMOS transistor adjacent the PMOS transistor in a channel width direction, a compressive stress liner overlying the PMOS transistor, and a tensile stress liner overlying the NMOS transistor. A portion of the compressive stress liner and a portion of the tensile stress liner are in a stacked configuration, and an overlap region of the compressive stress liner and the tensile stress liner is sufficient to result in an enhanced transverse stress in the compressive stress liner or the tensile stress liner.Type: GrantFiled: August 27, 2008Date of Patent: June 21, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Gen Pei, Scott D. Luning, Johannes van Meer
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Patent number: 9048136Abstract: A static random access memory cell is provided formed in a silicon layer over a buried oxide layer on a substrate and including first and second inverters each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters are formed over first regions below the buried oxide layer with the first regions having a first doping level forming first backgates for the pull-down transistors. A pair of passgate transistors respectively couples to the cell nodes of the first and second inverters and each are formed over second regions below the buried oxide layer with the second regions having a second doping level forming second backgates for the passgate transistors. Active bias circuitry applies potentials to the first and second backgates during read, standby and write operations of the static random access memory cell.Type: GrantFiled: October 26, 2011Date of Patent: June 2, 2015Assignee: GLOBALFOUNDRIES, INC.Inventors: Randy W. Mann, Scott D. Luning
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Patent number: 9029956Abstract: A static random access memory cell is provided that includes first and second inverters formed on a substrate each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters resides over first regions below the buried oxide layer and having a first doping level and applied bias providing a first voltage threshold for the pull-down transistors. A pair of passgate transistors is coupled the cell nodes of the first and second inverters, and each is formed over second regions below the buried oxide layer and having a second doping level and applied bias providing a second voltage threshold for the passgate transistors. The first voltage threshold differs from the second voltage threshold providing electrical voltage threshold control between the pull-down transistors and the passgate transistors.Type: GrantFiled: October 26, 2011Date of Patent: May 12, 2015Assignee: Global Foundries, Inc.Inventors: Randy W. Mann, Scott D. Luning
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Publication number: 20130107610Abstract: A static random access memory cell is provided that includes first and second inverters formed on a substrate each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters resides over first regions below the buried oxide layer and having a first doping level and applied bias providing a first voltage threshold for the pull-down transistors. A pair of passgate transistors is coupled the cell nodes of the first and second inverters, and each is formed over second regions below the buried oxide layer and having a second doping level and applied bias providing a second voltage threshold for the passgate transistors. The first voltage threshold differs from the second voltage threshold providing electrical voltage threshold control between the pull-down transistors and the passgate transistors.Type: ApplicationFiled: October 26, 2011Publication date: May 2, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Randy W. Mann, Scott D. Luning
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Publication number: 20130107608Abstract: A static random access memory cell is provided formed in a silicon layer over a buried oxide layer on a substrate and including first and second inverters each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters are formed over first regions below the buried oxide layer with the first regions having a first doping level forming first backgates for the pull-down transistors. A pair of passgate transistors respectively couples to the cell nodes of the first and second inverters and each are formed over second regions below the buried oxide layer with the second regions having a second doping level forming second backgates for the passgate transistors. Active bias circuitry applies potentials to the first and second backgates during read, standby and write operations of the static random access memory cell.Type: ApplicationFiled: October 26, 2011Publication date: May 2, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Randy W. Mann, Scott D. Luning
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Patent number: 7910996Abstract: A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.Type: GrantFiled: July 1, 2009Date of Patent: March 22, 2011Inventors: Paul R. Besser, Scott D. Luning
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Publication number: 20090267152Abstract: A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.Type: ApplicationFiled: July 1, 2009Publication date: October 29, 2009Applicant: Advanced Micro Devices, Inc.Inventors: Paul R. Besser, Scott D. Luning
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Publication number: 20090236664Abstract: A method for constraining lateral growth of gate caps formed during an epitaxial silicon growth process to achieve raised source/drain regions on poly silicon is presented. The method is appropriate for integration into a manufacturing process for integrated circuit semiconductor devices. The method utilizes selective etch processes, dependant upon the material comprising the protective layer (hard mask) over the gate and the material of the spacers, e.g., oxide mask/nitride spacers, or nitride mask/oxide spacers.Type: ApplicationFiled: May 26, 2009Publication date: September 24, 2009Applicant: ADVANCED MICRO DEVICES, INC.Inventors: David E. Brown, Scott D. Luning
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Patent number: 7572705Abstract: A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.Type: GrantFiled: September 21, 2005Date of Patent: August 11, 2009Assignee: Advanced Micro Devices, Inc.Inventors: Paul R. Besser, Scott D. Luning
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Patent number: 7553732Abstract: A method for constraining lateral growth of gate caps formed during an epitaxial silicon growth process to achieve raised source/drain regions on poly silicon is presented. The method is appropriate for integration into a manufacturing process for integrated circuit semiconductor devices. The method utilizes selective etch processes, dependant upon the material comprising the protective layer (hard mask) over the gate and the material of the spacers, e.g., oxide mask/nitride spacers, or nitride mask/oxide spacers.Type: GrantFiled: June 13, 2005Date of Patent: June 30, 2009Assignee: Advanced Micro Devices, Inc.Inventors: David E. Brown, Scott D. Luning
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Publication number: 20090008718Abstract: A CMOS circuit is provided that includes a PMOS transistor, an NMOS transistor adjacent the PMOS transistor in a channel width direction, a compressive stress liner overlying the PMOS transistor, and a tensile stress liner overlying the NMOS transistor. A portion of the compressive stress liner and a portion of the tensile stress liner are in a stacked configuration, and an overlap region of the compressive stress liner and the tensile stress liner is sufficient to result in an enhanced transverse stress in the compressive stress liner or the tensile stress liner.Type: ApplicationFiled: August 27, 2008Publication date: January 8, 2009Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Gen PEI, Scott D. LUNING, Johannes van MEER
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Patent number: 7442601Abstract: A stress enhanced CMOS circuit and methods for its fabrication are provided. One fabrication method comprises the steps of forming an NMOS transistor and a PMOS transistor adjacent the NMOS transistor in a channel width direction, the PMOS transistor and the NMOS transistor separated by an isolation region. A compressive stress liner is deposited overlying the transistors and the isolation region and is etched to remove the compressive stress liner from the NMOS transistor and from a portion of the isolation region. A tensile stress liner is deposited overlying the transistors, the isolation region, and the compressive stress liner and is etched to remove a portion of the tensile stress liner overlying a portion of the compressive stress liner and to leave the tensile stress liner overlying the NMOS transistor, the isolation region, and a portion of the compressive stress liner.Type: GrantFiled: September 18, 2006Date of Patent: October 28, 2008Assignee: Advanced Micro Devices, Inc.Inventors: Gen Pei, Scott D. Luning, Johannes van Meer
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Patent number: 7402485Abstract: A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.Type: GrantFiled: September 19, 2005Date of Patent: July 22, 2008Assignee: Advanced Micro Devices, Inc.Inventors: William G. En, Thorsten Kammler, Eric N. Paton, Scott D. Luning
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Publication number: 20080122002Abstract: A stress enhanced CMOS circuit and methods for its fabrication are provided. One fabrication method comprises the steps of forming an NMOS transistor and a PMOS transistor adjacent the NMOS transistor in a channel width direction, the PMOS transistor and the NMOS transistor separated by an isolation region. A compressive stress liner is deposited overlying the transistors and the isolation region and is etched to remove the compressive stress liner from the NMOS transistor and from a portion of the isolation region. A tensile stress liner is deposited overlying the transistors, the isolation region, and the compressive stress liner and is etched to remove a portion of the tensile stress liner overlying a portion of the compressive stress liner and to leave the tensile stress liner overlying the NMOS transistor, the isolation region, and a portion of the compressive stress liner.Type: ApplicationFiled: September 18, 2006Publication date: May 29, 2008Inventors: Gen Pei, Scott D. Luning, Johannes van Meer
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Patent number: 7241700Abstract: A gate structure is formed overlying a substrate. A source/drain region of the substrate is exposed to a soluction comprising ammonium hydroxide, hydrogen peroxide, and deionized water to etch an upper-most semiconductor porton of the source/drain region.Type: GrantFiled: October 20, 2004Date of Patent: July 10, 2007Assignee: Advanced Micro Devices, Inc.Inventors: William George En, Eric N. Paton, Scott D. Luning