Abstract: An example system includes first memory, second memory having a greater areal density than the first memory, and a logic circuit configured to move some test data from the second memory to the first memory while at least one of (i) reading other test data from the first memory or (ii) processing the other test data. The logic circuit is configured to process the other test data prior to output along a test channel. The test channel leads to a device under test (DUT) to be tested.

Abstract: A receiver circuit for a tester for electronic devices is provided. The receiver circuit includes a clock receiver that is adapted to receive a source synchronous clock signal from a device under test. The receiver circuit further includes a data receiver that is responsive to the clock circuit. The data receiver is adapted to receive at least one differential data signal from the device under test. The receiver circuit also includes a trigger receiver that is responsive to the clock circuit. The trigger receiver is adapted to receive a trigger signal from the device under test. Finally, the receiver circuit includes a control circuit that is coupled to the trigger receiver. The control circuit is adapted to generate a start alignment capture signal based on the received trigger signal to initiate capture of data received at the data receiver for comparison with expected values.

Abstract: A driver circuit for use on an integrated circuit tester. In one embodiment, the driver circuit has a timing circuit and a driver. The timing circuit has two or more inputs to receive data signals at a first frequency and at least one output. The timing circuit generates a control signal having a second higher frequency and outputs signals based on the data signals and the control signal such that the output signals are independent of the effects of timing skew and timing jitter of the data signals. The driver has at least one input coupled to the at least one output of the timing circuit to receive the output signals and couple the output signals to a device under test.

Abstract: A driver circuit for use on an integrated circuit tester. In one embodiment, the driver circuit has a timing circuit and a driver. The timing circuit has two or more inputs to receive data signals at a first frequency and at least one output. The timing circuit generates a control signal having a second higher frequency and outputs signals based on the data signals and the control signal such that the output signals are independent of the effects of timing skew and timing jitter of the data signals. The driver has at least one input coupled to the at least one output of the timing circuit to receive the output signals and couple the output signals to a device under test.

Abstract: A receiver circuit for a tester for electronic devices is provided. The receiver circuit includes a clock receiver that is adapted to receive a source synchronous clock signal from a device under test. The receiver circuit further includes a data receiver that is responsive to the clock circuit. The data receiver is adapted to receive at least one differential data signal from the device under test. The receiver circuit also includes a trigger receiver that is responsive to the clock circuit. The trigger receiver is adapted to receive a trigger signal from the device under test. Finally, the receiver circuit includes a control circuit that is coupled to the trigger receiver. The control circuit is adapted to generate a start alignment capture signal based on the received trigger signal to initiate capture of data received at the data receiver for comparison with expected values.

Abstract: An improved dynamic memory system including through-checking and error detection of the refresh counter is described. A refresh counter that provides parity of the refresh count for through-checking, of refresh addresses is shown. Error detecting circuitry is utilized in conjunction with the refresh counter and the parity generating circuitry to detect errors in functionality of the refresh counter. The refresh counter is a Gray code counter constructed of a double rank of latches operable with code generating logic circuits for determining the sequence of generation of Gray code groupings.

Abstract: An improved error indicating system utilizing adder circuits for use with an error correction code system capable of detecting and indicating multiple bit errors and detecting and correcting single bit errors is described. The system utilizes an encoding system for generating a plurality of check bits, each check bit associated with a predetermined bit grouping of data bits within a data word. When a data word is accessed, read check bits are reconstituted from the read data and are compared to the check bits originally encoded. Syndrome bits are generated from the originally encoded check bits and the reconstituted read check bits, the syndrome bits thus generated, serving to identify whether the data word accessed contains no errors, a single bit error, or a multiple bit error. Decoder circuitry for decoding the syndrome bits and effecting the control signals for controlling the correction of single bit errors is described.

Abstract: A method of and an apparatus for differentiating between hard and soft failures of semiconductor memory cells for the purpose of error logging only hard failures. A spare bit position is appended to each addressable location within the semiconductor memory. The spare bit position is set, if the corresponding addressable location is observed to contain a single bit error during regeneration. The spare bit position is cleared, if the corresponding addressable location is observed not to contain a single bit error during regeneration. An error log entry is made for normal read access to an addressable location observed to contain a single bit error only if the spare bit is set indicating that a single bit error was present during regeneration of that addressable location.