Abstract: Techniques are described for implementing read-out architectures to support high-speed serialized read-out of a large number of digital bit values, such as for high-resolution pixel conversions in CMOS image sensor applications. For example, outputs from a large number of digital data sources (e.g., counters) are coupled with transmission gates of the read-out architecture, and the transmission gates are sequentially enabled, thereby shifting in bit data from the data sources one at a time. The transmission gates are grouped into gate groups. For each gate group, embodiments seek balance total path delay across the gate groups by controlling clock and data path delays to be inversely related, and ensuring that total path delays for all gate groups are within a single clock period. Some embodiments include a partitioned bus for further gate group-level control over the path delay and data bus capacitance.

Abstract: Techniques are described for sampled bandgap reference generation for CMOS image sensor (CIS) applications. For example, the CIS includes a pixel array, one or more pixel analog to digital converters (ADCs), and a sampled bandgap reference generator, all integrated in close proximity on a chip. The ADCs rely on stable reference levels from the bandgap reference generator for performing pixel conversions for the pixel array. Embodiments of the sampled bandgap reference generator can operate according to reference generation cycles. Each cycle can include a first portion, in which an active core dynamically stabilizes the bandgap reference level; and a second portion, in which the core is deactivated, and the bandgap reference level is output based on a sampled level obtained during the preceding first portion of the cycle. The cycle timing can be controlled to achieve sufficient dynamic stabilization of the reference levels, while mitigating photon emissions from the core.

Abstract: Techniques are described for implementing read-out architectures to support high-speed serialized read-out of a large number of digital bit values, such as for high-resolution pixel conversions in CMOS image sensor applications. For example, outputs from a large number of digital data sources (e.g., counters) are coupled with transmission gates of the read-out architecture, and the transmission gates are sequentially enabled, thereby shifting in bit data from the data sources one at a time. The transmission gates are grouped into gate groups. For each gate group, embodiments seek balance total path delay across the gate groups by controlling clock and data path delays to be inversely related, and ensuring that total path delays for all gate groups are within a single clock period. Some embodiments include a partitioned bus for further gate group-level control over the path delay and data bus capacitance.

Abstract: An image sensor includes a pixel array comprising a plurality of pixels, a color filter array comprising a plurality of color filter clusters overlying the pixel array, and readout circuitry configured to concurrently provide the pixels sharing the common filter cluster and having a first exposure time to a readout line for digital data conversion. Each of the color filter clusters includes a group of same color filters, and pixels sharing a common color filter cluster have different exposure times.

Abstract: An image sensor includes a pixel array comprising a plurality of pixels, a color filter array comprising a plurality of color filter clusters overlying the pixel array, and readout circuitry configured to concurrently provide the pixels sharing the common filter cluster and having a first exposure time to a readout line for digital data conversion. Each of the color filter clusters includes a group of same color filters, and pixels sharing a common color filter cluster have different exposure times.

Abstract: Techniques are described for implementing counter architectures to support high-speed, high-resolution pixel conversions, such as for CMOS image sensor applications. Embodiments implement a counter block that uses loadable true-signal-phase-clocking (L-TSPC) flops for at least a portion of the counter flops. Some embodiments support efficient two-phase pixel conversion by integrating counting, subtraction, and shifting out in the counter. For example, embodiments can perform a first high-speed pixel conversion phase to obtain a first conversion count. Prior to a second phase, the initial counter can be pre-subtracted by the amount of the first conversion count. Embodiments can then perform a second high-speed pixel conversion phase to obtain a second conversion count. As the second conversion count already has the first conversion count pre-subtracted, the second conversion count represents the final two-phase conversion result.

Abstract: An image sensor includes a controller and a plurality of pixel clusters. Each of the pixel clusters includes a plurality of pixels coupled to a reset transistor, a floating diffusion node, a source follower, and a select transistor. Each pixel of a pixel cluster includes a photodiode, and a transfer transistor having a first terminal coupled to the photodiode, a second terminal coupled to the floating diffusion node, and a gate. The controller is configured to apply a transfer control signal to the gate of the transfer transistor in response to a pixel operation, the transfer control signal being one of a positive voltage level, a negative voltage level, and a ground voltage level.

Abstract: An image sensor includes a pixel array comprising a plurality of pixels, a color filter array comprising a plurality of color filter clusters overlying the pixel array, and readout circuitry configured to concurrently provide the pixels sharing the common filter cluster and having a first exposure time to a readout line for digital data conversion. Each of the color filter clusters includes a group of same color filters, and pixels sharing a common color filter cluster have different exposure times.

Abstract: An image sensor includes a pixel array comprising a plurality of pixels, a color filter array comprising a plurality of color filter clusters overlying the pixel array, and readout circuitry configured to concurrently provide the pixels sharing the common filter cluster and having a first exposure time to a readout line for digital data conversion. Each of the color filter clusters includes a group of same color filters, and pixels sharing a common color filter cluster have different exposure times.

Abstract: An image sensor includes a controller and a plurality of pixel clusters. Each of the pixel clusters includes a plurality of pixels coupled to a reset transistor, a floating diffusion node, a source follower, and a select transistor. Each pixel of a pixel cluster includes a photodiode, and a transfer transistor having a first terminal coupled to the photodiode, a second terminal coupled to the floating diffusion node, and a gate. The controller is configured to apply a transfer control signal to the gate of the transfer transistor in response to a pixel operation, the transfer control signal being one of a positive voltage level, a negative voltage level, and a ground voltage level.

Abstract: A band gap circuit with offset voltage error correction including a diode junction circuit, an error amplifier, a current device, a bias current generator, a calibration circuit, and a mode control circuit. During a normal mode of operation, the error amplifier monitors feedback nodes of the diode junction circuit and drives the current device to provide a control current to the diode junction circuit. During a calibration mode, the current device is decoupled from the diode junction circuit and the inputs of the error amplifier are shorted together, the bias generator circuit sinks a bias current from the current device and separately sources a bias current to the diode junction circuit such that the error amplifier operates as a comparator, and the calibration circuit monitors the output of the current device while adjusting a trim current of the error amplifier to minimize an offset voltage error of the error amplifier.

Abstract: A band gap circuit with offset voltage error correction including a diode junction circuit, an error amplifier, a current device, a bias current generator, a calibration circuit, and a mode control circuit. During a normal mode of operation, the error amplifier monitors feedback nodes of the diode junction circuit and drives the current device to provide a control current to the diode junction circuit. During a calibration mode, the current device is decoupled from the diode junction circuit and the inputs of the error amplifier are shorted together, the bias generator circuit sinks a bias current from the current device and separately sources a bias current to the diode junction circuit such that the error amplifier operates as a comparator, and the calibration circuit monitors the output of the current device while adjusting a trim current of the error amplifier to minimize an offset voltage error of the error amplifier.

Abstract: A long-wave or medium-wave receiver receives a first signal from a first terminal of a loopstick antenna on a positive antenna input terminal of the receiver and receives a second signal from a second terminal of the loopstick antenna on a negative antenna input terminal of the receiver. The first and second signals are processed differentially in the receiver. The receiver may optionally be configured to operate in either a differential mode or a single-ended mode by setting switches to selectively connect one of the antenna input terminals to ground in single-ended mode.

Abstract: In one embodiment, the present invention includes a method for configuring a single chip radio tuner having a configurable front end, which may be adapted within an integrated circuit (IC). The method may include setting a controller of the tuner with configuration information for a radio in which the tuner is located. Then, control signals responsive to the configuration information can be sent to the configurable front end to configure the tuner.

Abstract: A long-wave or medium-wave receiver receives a first signal from a first terminal of a loopstick antenna on a positive antenna input terminal of the receiver and receives a second signal from a second terminal of the loopstick antenna on a negative antenna input terminal of the receiver. The first and second signals are processed differentially in the receiver. The receiver may optionally be configured to operate in either a differential mode or a single-ended mode by setting switches to selectively connect one of the antenna input terminals to ground in single-ended mode.

Abstract: In one embodiment, the present invention includes a method for configuring a single chip radio tuner having a configurable front end, which may be adapted within an integrated circuit (IC). The method may include setting a controller of the tuner with configuration information for a radio in which the tuner is located. Then, control signals responsive to the configuration information can be sent to the configurable front end to configure the tuner.

Abstract: In one embodiment, the present invention includes a method for configuring a single chip radio tuner having a configurable front end, which may be adapted within an integrated circuit (IC). The method may include setting a controller of the tuner with configuration information for a radio in which the tuner is located. Then, control signals responsive to the configuration information can be sent to the configurable front end to configure the tuner.

Abstract: In one embodiment, the present invention includes a single chip radio tuner, which may be adapted within an integrated circuit (IC). The tuner may be provided with a configurable front end to receive and process a radio frequency (RF) signal via a signal path. This configurable front end may be differently controlled depending on a particular radio implementation in which the tuner is adapted.

Abstract: In one embodiment, the present invention includes a single chip radio tuner, which may be adapted within an integrated circuit (IC). The tuner may be provided with a configurable front end to receive and process a radio frequency (RF) signal via a signal path. This configurable front end may be differently controlled depending on a particular radio implementation in which the tuner is adapted.

Abstract: In one embodiment, the present invention includes a method for configuring a single chip radio tuner having a configurable front end, which may be adapted within an integrated circuit (IC). The method may include setting a controller of the tuner with configuration information for a radio in which the tuner is located. Then, control signals responsive to the configuration information can be sent to the configurable front end to configure the tuner.