Patents by Inventor Scott Darren White

Scott Darren White has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Electronic circuits
    Patent number: 9768782
    Abstract: An electronic circuit comprises: an input terminal; an output terminal; first and second supply rails; first, second, third, and fourth field effect transistors, FETs, each of a first type and each having respective gate, source and drain terminals; and first and second loads. The source of the first FET is connected to the first supply rail, the drain of the first FET and the source of the second FET are connected to the output terminal, the drain of the second FET is connected to the second supply rail, the gate of the third FET and the gate of the fourth FET are connected to the input terminal, the drain of the third FET is connected to the second supply rail, the first load is connected between the first supply rail and the source of the third FET, and the second load is connected between the drain of the fourth FET and the second supply rail.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: September 19, 2017
    Assignee: Pragmatic Printing Limited
    Inventors: Joao de Oliveira, Scott Darren White, Catherine Ramsdale
  • ELECTRONIC CIRCUITS
    Publication number: 20160173099
    Abstract: An electronic circuit comprises: an input terminal; an output terminal; first and second supply rails; first, second, third, and fourth field effect transistors, FETs, each of a first type and each having respective gate, source and drain terminals; and first and second loads. The source of the first FET is connected to the first supply rail, the drain of the first FET and the source of the second FET are connected to the output terminal, the drain of the second FET is connected to the second supply rail, the gate of the third FET and the gate of the fourth FET are connected to the input terminal, the drain of the third FET is connected to the second supply rail, the first load is connected between the first supply rail and the source of the third FET, and the second load is connected between the drain of the fourth FET and the second supply rail.
    Type: Application
    Filed: July 16, 2014
    Publication date: June 16, 2016
    Applicant: Pragmatic Printing Ltd
    Inventors: Joao de Oliveira, Scott Darren White, Catherine Ramsdale