Abstract: Systems and methods are provided herein for operating a conveyance system (e.g., a conveyor belt, tilt plane, robotic arm) of a mobile drive unit (MDU) independent of the MDU's navigation system. The MDU may be configured to obtain, convey, and deliver items within the workspace. Navigation information related to navigating the MDU within a workspace may be obtained. Operations of a navigational system of the MDU may be performed to move the MDU to various locations within the workspace in accordance with the navigation information. Conveyance information related to physically obtaining and/or delivering an item within the workspace may be obtained by the MDU (e.g., via conveyance-related fiducial markers and/or sensors of the MDU). At least one operation of a conveyance system of the MDU may be executed which may cause the item to be physically relocated based at least in part on the conveyance information.

Abstract: Systems and methods are provided herein for operating a conveyance system (e.g., a conveyor belt, tilt plane, robotic arm) of a mobile drive unit (MDU) independent of the MDU's navigation system. The MDU may be configured to obtain, convey, and deliver items within the workspace. Navigation information related to navigating the MDU within a workspace may be obtained. Operations of a navigational system of the MDU may be performed to move the MDU to various locations within the workspace in accordance with the navigation information. Conveyance information related to physically obtaining and/or delivering an item within the workspace may be obtained by the MDU (e.g., via conveyance-related fiducial markers and/or sensors of the MDU). At least one operation of a conveyance system of the MDU may be executed which may cause the item to be physically relocated based at least in part on the conveyance information.

Abstract: A transfer rack on one floor of an inventory system can receive multiple containers each carrying an inventory item designated for an operation on a different floor of the inventory system. A vertical lift can move the transfer rack carrying the multiple containers from the one floor to the different floor. On the different floor, the multiple containers may be swapped for different multiple containers each carrying an inventory item designated for an operation on the one floor. The vertical lift may return the transfer rack carrying the different multiple containers to the one floor.

Abstract: Item information such as an identity or arrangement of a selected inventory item of an inventory system can be determined. A classification of the selected inventory item can be obtained based at least in part on the item information. The selected inventory item can be routed based at least in part on the classification of the selected inventory item. For example, the selected inventory item may be routed for manual handling if the classification of the selected inventory item indicates that the selected inventory item is designated for an operation to be performed relative to the selected inventory item by a human operator. Alternatively, the selected inventory item may be routed for automated handling if the classification of the selected inventory item indicates that the selected inventory item is designated for an operation to be performed relative to the selected inventory item by a robotic manipulator.

Abstract: A transfer rack on one floor of an inventory system can receive multiple containers each carrying an inventory item designated for an operation on a different floor of the inventory system. A vertical lift can move the transfer rack carrying the multiple containers from the one floor to the different floor. On the different floor, the multiple containers may be swapped for different multiple containers each carrying an inventory item designated for an operation on the one floor. The vertical lift may return the transfer rack carrying the different multiple containers to the one floor.

Abstract: An apparatus is provided for determining a configuration of memory modules. Each of the memory modules produces presence detect bits. In a first feature, the apparatus includes an external register for receiving the presence detect bits from the memory modules in parallel and a memory controller integrated circuit. The memory controller integrated circuit includes an internal register for storing the presence detect bits and logic circuitry for determining a memory configuration. The presence detect bits are serially transferred from the external register to the internal register. In a second feature, the logic circuitry for determining a memory configuration includes comparator circuitry for comparing the presence detect bits of each pair of memory modules and generating a match signal or a mismatch signal. When a match signal occurs, the presence detect bits of the memory module pair are loaded into a memory configuration register.

Abstract: A memory controller for controlling access to a memory includes a circuit for generating memory signals, including address and control signals, for accessing a memory in response to a physical address, and a circuit for programming the timing of the memory signals in response to predetermined timing control information which defines the timing requirements of the memory. The circuit for programming the timing of the memory preferably includes a register for storing timing control bits and selectors responsive to the timing control bits for selecting timing control parameters from a group of predetermined timing control parameters. The circuit for programming the timing preferably further includes a circuit responsive to each timing control parameter and to a selected memory signal for generating a timing control signal. The timing control signal controls the timing of one of the memory signals.

Abstract: A memory controller for controlling access to a memory includes a mapper for mapping a physical address to a row address and a column address that are suitable for addressing first and second memory devices having the same memory capacity but different addressing formats, a multiplexer for multiplexing the row address and the column address onto a set of address lines for addressing the memory and a circuit for generating control signals for controlling access to the memory. In a preferred embodiment, the first memory devices are 16 Mb DRAMs which require asymmetric addressing, and the second memory devices are 16 Mb DRAMs which require symmetric addressing. The memory controller of the invention generates a row address and a column address for addressing both types of memory devices without having knowledge of the types of memory devices that are present in the memory.