Abstract: A phase-locked oscillator (PLO) driven or derived clock system, the frequency of which is higher by a factor N than the frequency of the bit reference clock of incoming streams of data bits. The derived clock is designed to be maintained in synchronism with the bit reference clock. Two counters are provided, both of which are driven by the derived clock. The reference counter counts to N/2 and outputs a pulse. The other counter counts to N, outputs a pulse and starts again. The two counters provide output pulses which are coincident whenever the derived or PLO clock is in synchronism with the data clock. This is determined by a phase detector which includes a pair of identical latches, each of which is set by one of the two counters. The outputs of the latches go to an AND gate, the output of which resets the latches. The outputs on the two Q leads from the latches go to an amplifier which outputs a signal which is other than zero, only when there is lack of synchronism.