Abstract: Automatic part testing includes: booting a part under testing into a first operating environment; executing, via the first operating environment, one or more test patterns on the part; performing a comparison between one or more observed characteristics associated with the one or more test patterns and one or more expected characteristics; and modifying one or more operational parameters of a central processing unit of the part based on the comparison.

Abstract: Automatic part testing includes: booting a part under testing into a first operating environment; executing, via the first operating environment, one or more test patterns on the part; performing a comparison between one or more observed characteristics associated with the one or more test patterns and one or more expected characteristics; and modifying one or more operational parameters of a central processing unit of the part based on the comparison.

Abstract: Automatic part testing includes: booting a part under testing into a first operating environment; executing, via the first operating environment, one or more test patterns on the part; performing a comparison between one or more observed characteristics associated with the one or more test patterns and one or more expected characteristics; and modifying one or more operational parameters of a central processing unit of the part based on the comparison.

Abstract: Automatic part testing includes: booting a part under testing into a first operating environment; executing, via the first operating environment, one or more test patterns on the part; performing a comparison between one or more observed characteristics associated with the one or more test patterns and one or more expected characteristics; and modifying one or more operational parameters of a central processing unit of the part based on the comparison.

Abstract: A serial communication system includes an integrated circuit having a master serial interface; and a processor having a slave serial interface coupled to the master serial interface through a clock signal line and a data signal line. The slave serial interface is responsive to a read temperature command issued by the master serial interface to return a first temperature value associated with the processor.

Abstract: A message based power management approach is utilized to provide power management for a multi-processor system. A power management message is received at one processor of the multi-processor system over an input/output communication link that provides input/output access for the processors of the multi-processor system. The power management message includes a power management field encoding a power management state for processors of the multi-processor system. The processor that received the power management message over the input/output communication link sends a power management message to other processors in the multi-processor system over one or more inter-processor communication links encoding the power management state.

Abstract: An integrated circuit is coupled to a communication link and to a separate signal line and includes programmable registers specifying communication link width and frequency. The integrated circuit responds to a change in the value of the signal line by changing the width and/or frequency of at least a portion of the communication link to the programmed value in response to a change in a logical value of the signal line, without the integrated circuit entering a reset state. The width and/or frequency may be changed during a POST routine or during system operation as part of a power management or other system function while maintaining its operational state.

Abstract: A message based power management system converts legacy signals used in power management, and other signals used to differentiate between power states, to messages sent over a communication link. A system message sent on a communication link includes a field encoding the level of power management for the device receiving the system message. Further, one or more additional signals, separate from the communication link, may be used to indicate when to take action after the power management message has been received.

Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and may also include a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes byte slicing and/or data packing logic coupled to one or more of the expansion bus and/or the multimedia bus which operates to allow different data streams to use different byte channels simultaneously. Thus the byte sliced bus allows different peripherals to share the bus simultaneously. The byte slicing logic thus may assign one data stream to a subset of the total byte lanes on the multimedia bus, and fill the unused byte lanes with another data stream. The data packing logic may optimally fill the bus with data having more or fewer bits than the bus.

Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and may also include a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes byte slicing logic coupled to one or more of the expansion bus and/or the multimedia bus which operates to allow different data streams to use different byte channels simultaneously. Thus the byte sliced multimedia bus allows different peripherals to share the bus simultaneously. The byte slicing logic thus may assign one data stream to a subset of the total byte lanes on the multimedia bus, and fill the unused byte lanes with another data stream. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.

Abstract: A computer chip including multiple on-chip modules connected by an on-chip bus which provides increased performance over current computer chip architectures. The on-chip system bus is a bit sliced bus. Various transmitters/and or receivers are coupled the bit sliced bus. The transmitters and/or receivers include bus interface logic and/or bit transfer logic and/or bit receive logic operatively coupled to the on-chip bit sliced bus which operates to allow different data streams to use different bit lines substantially simultaneously. Thus the bit sliced bus allows different devices to share the bus simultaneously. The bus interface logic and/or the bit transfer logic thus may assign one data stream to a subset of the total bit lines on the bit sliced bus, and fill the unused bit lines with another data stream.

Abstract: A computer system is provided for controlling the ownership of a bus to which a variety of both real time and non-real time resources are coupled. The bus arbiter includes a request detection unit for detecting bus request signals of a plurality of bus masters, and a grant generator for generating corresponding grant signals to indicate a grant of ownership of the bus. A set of counters referred to as "request latency" counters is further provided wherein a separate counter unit corresponds to each bus master. Each counter is configured to generate a signal indicative of a lapse of time since a time when the peripheral requested ownership of the bus. An arbitration control unit is coupled to the request latency counters, the request detection unit and the grant generator for processing incoming bus request signals. The arbitration control unit is configured to dynamically vary the level of arbitration priority given to each peripheral device based upon the latency signal corresponding to the device.

Abstract: An interrupt polling unit included within a bus interface unit of a microprocessor is provided. The interrupt polling unit causes an interrupt acknowledge bus transaction to occur. If an interrupt controller receiving the interrupt acknowledge bus transaction returns an interrupt vector indicative of an interrupt service routine, then the microprocessor executes the interrupt service routine. The number of interrupt acknowledge bus transactions associated with the interrupt is reduced from two to one. In one embodiment, the interrupt polling unit causes an interrupt acknowledge bus transaction to occur when the microprocessor is performing a task switch. The task switch may be performed by hardware included within the microprocessor or, alternatively, by software executing upon the microprocessor.

Abstract: An interrupt polling unit included within a bus interface unit of a microprocessor is provided. The interrupt polling unit causes a periodic interrupt acknowledge bus transaction to occur. If an interrupt controller receiving the interrupt acknowledge bus transaction returns an interrupt vector indicative of an interrupt service routine, then the microprocessor executes the interrupt service routine. The number of interrupt acknowledge bus transactions associated with the interrupt is reduced from two to one, and the microprocessor effectively prefetches the interrupt service routine before the interrupt is actually signaled. In one embodiment, the interrupt polling unit causes an interrupt acknowledge bus transaction to occur at the expiration of a programmable time interval. Another embodiment of the interrupt polling unit causes an interrupt acknowledge bus transaction subsequent to the occurrence of a bus transaction programmed by the user.