Patents by Inventor Scott F. James

Scott F. James has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CAVLC run before encode with zero cycle costs
    Patent number: 8135072
    Abstract: An apparatus including a control circuit and an encoder circuit. The control circuit may configured to generate a first control signal and a second control signal. The encoder circuit may be configured to (i) receive a plurality of coefficients, the first control signal and the second control signal and (ii) generate an encoded signal in response to the plurality of coefficients, the first control signal and the second control signal. The encoder circuit may be further configured to simultaneously encode run before syntax elements with the plurality of coefficients.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: March 13, 2012
    Assignee: LSI Corporation
    Inventors: Scott F. James, Eric C. Pearson
  • CAVLC run before encode with zero cycle costs
    Publication number: 20090034611
    Abstract: An apparatus including a control circuit and an encoder circuit. The control circuit may configured to generate a first control signal and a second control signal. The encoder circuit may be configured to (i) receive a plurality of coefficients, the first control signal and the second control signal and (ii) generate an encoded signal in response to the plurality of coefficients, the first control signal and the second control signal. The encoder circuit may be further configured to simultaneously encode run before syntax elements with the plurality of coefficients.
    Type: Application
    Filed: March 28, 2008
    Publication date: February 5, 2009
    Inventors: Scott F. James, Eric C. Pearson
  • Arithmetic decode without renormalization costs
    Patent number: 7397401
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate context information in response to one or more bins on a binary signal. The second circuit may be configured to generate the binary signal in response to (i) one or more input bits on a bitstream signal, and (ii) simultaneously performing in a single cycle (a) an arithmetic decode of the context information and (b) a renormalization of the context information.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: July 8, 2008
    Assignee: LSI Logic Corporation
    Inventors: Harminder S. Banwait, Eric C. Pearson, Scott F. James
  • Arithmetic decode without renormalization costs
    Publication number: 20080007436
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate context information in response to one or more bins on a binary signal. The second circuit may be configured to generate the binary signal in response to (i) one or more input bits on a bitstream signal, and (ii) simultaneously performing in a single cycle (a) an arithmetic decode of the context information and (b) a renormalization of the context information.
    Type: Application
    Filed: July 7, 2006
    Publication date: January 10, 2008
    Inventors: Harminder S. Banwait, Eric C. Pearson, Scott F. James