Abstract: A computer-implemented system and method for performing video compression are described.

Abstract: A computer-implemented system and method are described for encoding video. For example, a method according to one embodiment comprises: selecting a tile size for subdividing each image in a sequence of images based on a specified type of encoding algorithm to be used for encoding the tiles, wherein M tiles are encoded for each image, each tile being encoded according to a first encoding format or a second encoding format, each tile having a designated tile location within each image; specifying a rotating pattern to be used for encoding the tiles over a sequence of N images, the rotating pattern comprising encoding only certain tiles of each image using the first encoding format, and rotating the tile locations selected for the first encoding format over the N images to ensure that all M tiles have been encoded according to the first encoding format across the N images; and encoding the sequence of N images using the rotating pattern.

Abstract: A computer-implemented system and method are described for managing the state of an online video game. For example, a method according to one embodiment comprises: initiating a new online video game in response to user input from a client device, the online video game being in a first state on a first server when initiated; executing the online video game on the server, thereby causing the online video game to enter into a second state; pausing or terminating the online video game; determining differences between the first state and the second state and generating difference data containing the differences; transmitting the difference data over a network to a second server, the second server; and recreating the second state from the difference data and the first state in response to user input indicating that the user wishes to resume the online video game and in response to the second server being selected as the server on which to execute the video game.

Abstract: A computer-implemented system and method are described for performing video compression. For example, a method according to one embodiment comprises: encoding a plurality of video frames or portions thereof according to a first encoding format; transmitting the plurality of encoded video frames or portions to a client device; receiving feedback information from the client device, the feedback information usable to determine whether data contained in the video frames or portions has not been successfully received and/or decoded; in response to detecting that a video frame or portion thereof has not been successfully received and/or decoded, encoding a video frame or portion thereof according to a second encoding format; and transmitting the video frames or portions thereof to the client device.

Abstract: A computer-implemented system and method for performing video compression are described.

Abstract: A computer-implemented system and method are described for online gaming.

Abstract: A computer-implemented system and method for streaming video from a server to a client are described. For example, a method according to one embodiment comprises: receiving at the server a request for video content from the client; in response to the request, determining the hardware/software configuration of the client; generating and/or selecting a temporary decoder based on the hardware/software configuration of the client; transmitting the temporary decoder to the client, the client installing the temporary decoder; encoding and streaming the requested video content from the server to the client, the video content being encoded based on the capabilities of the temporary decoder, the video content being decoded by the temporary decoder and rendered on the client; detecting that the client has ended the session with the server; and in response to detecting that the client has ended the session, temporarily disabling and/or removing the temporary decoder from the client.

Abstract: Apparatus having corresponding methods and computer-readable media comprise a receiver adapted to receive a plurality of single-frequency network (SFN) signals at a predetermined frequency; a correlator adapted to correlate the SFN signals with a predetermined reference signal, wherein correlating produces a plurality of correlation peaks; a grouper circuit adapted to group the correlation peaks into arrival groups such that the correlation peaks in different arrival groups are known to be from different transmitters; and a selection circuit adapted to select the earliest correlation peak in each arrival group as a leading correlation peak.

Abstract: Apparatus having corresponding methods and computer-readable media comprise an input circuit to receive a transport stream of data, wherein the transport stream has periodic synchronization boundaries; a signal generator to provide a ranging signal, wherein the ranging signal represents a transmitter identifier; and a ranging time slice inserter to insert ranging time slices into the transport stream, wherein each ranging time slice is inserted into the transport stream at the same predetermined offset from a respective one of the periodic synchronization boundaries, and wherein each ranging time slice includes the ranging signal.

Abstract: Apparatus having corresponding methods and computer-readable media comprises a receiver to receive a wireless stereo frequency-modulation (FM) signal comprising a plurality of spectral signal components including a first tone and one or more frequency bands; one or more tone generators each to generate a respective second tone based on a respective one of the frequency bands; a plurality of phase circuits each to measure a phase of a respective one of the first and second tones; and a difference element to determine a phase difference between two of the phases.

Abstract: Systems, apparatus, methods and computer program products are provided for causing a dataframe to be emitted at an air interface of an antenna. A memory stores a transmission to antenna delay value (TAD). An offset calculator calculates an offset value based on an epoch of a global timebase generator and the transmission to antenna delay value (TAD). An interface controller in communication with the offset calculator communicates a segment synchronization signal and a field synchronization signal based on the offset value.

Abstract: Apparatus having corresponding methods and computer-readable media comprises a receiver to receive a wireless stereo frequency-modulation (FM) signal comprising a plurality of spectral signal components including a first tone and one or more frequency bands; one or more tone generators each to generate a respective second tone based on a respective one of the frequency bands; a plurality of phase circuits each to measure a phase of a respective one of the first and second tones; and a difference element to determine a phase difference between two of the phases.

Abstract: A coating solution for providing a corrosion resistant coating to a metal surface including: a water soluble silicate; and at least one metal ion (X) selected from those having a valence of less than or equal to +4; wherein said coating solution forms an aqueous silicate-X network such that the silicate remains soluble, and wherein on contact with a metal surface (Y) a coating comprising of silicate-X and Y is formed.

Abstract: A sprite engine or compositor that is well-adapted to a variety ofadaptable to a host platforms and that minimizes the amount of drawing that occurs on a refresh of a framebuffer display area. The invention exploits the host platform's abilities to perform both back-to-front and front-to-back drawing algorithms, where the choice of algorithm used depends upon whether a sprite is opaque or transparent. Each sprite registers itself with a sprite engine, identifying whether or not the sprite is wholly opaque or notis transparent, the bounding area of the sprite, and the function that the sprite uses to draw. The function can be the drawing routine that is available from the host platform or operating system. The sprite engine keeps track of the Z position of each sprite and examines each sprite to determine if the sprite overlaps a particular region that needs to be refreshed.

Abstract: A non-blocking load buffer is provided for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects to peripheral devices. The non-blocking load buffer allows data to be retrieved from relatively low bandwidth peripheral devices directly from programmed I/O of the processor at the maximum rate of the peripherals so that the data may be processed and stored without unnecessarily idling the processor. I/O requests from several processors within a multiprocessor may simultaneously be buffered so that a plurality of non-blocking loads may be processed during the latency period of the device. As a result, a continuous maximum throughput from multiple I/O devices by the programmed I/O of the processor is achieved and the time required for completing tasks and processing data may be reduced.

Abstract: A non-blocking load buffer for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects to peripheral devices. The non-blocking load buffer allows data to be retrieved from relatively low bandwidth peripheral devices directly from programmed I/O of the processor at the maximum rate of the peripherals so that the data may be processed and stored without unnecessarily idling the processor. I/O requests from several processors within a multiprocessor may simultaneously be buffered so that a plurality of non-blocking loads may be processed during the latency period of the device. As a result, a continuous maximum throughput from multiple I/O devices by the programmed I/O of the processor is achieved and the time required for completing tasks and processing data may be reduced.

Abstract: A non-blocking load buffer is provided for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects to peripheral devices. The non-blocking load buffer allows data to be retrieved from relatively low bandwidth peripheral devices directly from programmed I/O of the processor at the maximum rate of the peripherals so that the data may be processed and stored without unnecessarily idling the processor. I/O requests from several processors within a multiprocessor may simultaneously be buffered so that a plurality of non-blocking loads may be processed during the latency period of the device. As a result, a continuous maximum throughput from multiple I/O devices by the programmed I/O of the processor is achieved and the time required for completing tasks and processing data may be reduced.