Patents by Inventor Scott G. Gibbons

Scott G. Gibbons has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Co-prime division prescaler and frequency synthesizer
    Patent number: 6845139
    Abstract: A system may include a control unit and a dual modulus prescaler. The control unit may generate a modulus control signal. The dual modulus prescaler may be configured to divide the frequency of an input signal by Q when the modulus control signal has a first value and to divide the frequency of the input signal by (Q+V) when the modulus control signal has a second value. Q is an irreducible fraction. The sum (Q+V) may be an integer or a fraction. The dual-modulus prescaler includes several clocked storage units (e.g., flip-flops) that are each clocked by a respective one of several equally spaced phases of the input signal. Each clocked storage unit operates in a toggle mode.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: January 18, 2005
    Assignee: DSP Group, Inc.
    Inventor: Scott G. Gibbons
  • Co-prime division prescaler and frequency synthesizer
    Publication number: 20040036513
    Abstract: A system may include a control unit and a dual modulus prescaler. The control unit may generate a modulus control signal. The dual modulus prescaler may be configured to divide the frequency of an input signal by Q when the modulus control signal has a first value and to divide the frequency of the input signal by (Q+V) when the modulus control signal has a second value. Q is an irreducible fraction. The sum (Q+V) may be an integer or a fraction. The dual-modulus prescaler includes several clocked storage units (e.g., flip-flops) that are each clocked by a respective one of several equally spaced phases of the input signal. Each clocked storage unit operates in a toggle mode.
    Type: Application
    Filed: August 23, 2002
    Publication date: February 26, 2004
    Inventor: Scott G. Gibbons
  • Methods and apparatus for alteration of terminal counts of phase-locked loops
    Patent number: 6597246
    Abstract: A phase-locked loop (PLL) includes a down counter having a detection circuit configured to determine when the counter reaches its terminal count. The down counter also includes a control line configured to alter the terminal count detected by the detection circuit by an off-set.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: July 22, 2003
    Assignee: DSP Group, Inc.
    Inventors: Eric L. Unruh, Scott G. Gibbons
  • Methods and apparatus for alteration of terminal counts of phase-locked loops
    Publication number: 20020167359
    Abstract: A phase-locked loop (PLL) includes a down counter having a detection circuit configured to determine when the counter reaches its terminal count. The down counter also includes a control line configured to alter the terminal count detected by the detection circuit by an off-set.
    Type: Application
    Filed: May 14, 2001
    Publication date: November 14, 2002
    Inventors: Eric L. Unruh, Scott G. Gibbons