Patents by Inventor Scott Hilker

Scott Hilker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170147288
    Abstract: A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bit-shifting circuit that is communicatively coupled to the first, second and third precision operation circuits. A method is also provided for multiplying a first and second binary number including adding a first exponent value associated with the first binary number to a second exponent value associated with the second binary number and multiplying a first mantissa value associated with the first binary number to a second mantissa value associated with the second binary number. The method includes performing the exponent adding and mantissa multiplying substantially in parallel. The method further includes performing at least one of adding or subtracting a third binary number to the product. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus.
    Type: Application
    Filed: December 27, 2016
    Publication date: May 25, 2017
    Inventor: Scott Hilker
  • Patent number: 9557963
    Abstract: A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bit-shifting circuit that is communicatively coupled to the first, second and third precision operation circuits. A method is also provided for multiplying a first and second binary number including adding a first exponent value associated with the first binary number to a second exponent value associated with the second binary number and multiplying a first mantissa value associated with the first binary number to a second mantissa value associated with the second binary number. The method includes performing the exponent adding and mantissa multiplying substantially in parallel. The method further includes performing at least one of adding or subtracting a third binary number to the product. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: January 31, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Scott Hilker
  • Publication number: 20150347090
    Abstract: A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bit-shifting circuit that is communicatively coupled to the first, second and third precision operation circuits. A method is also provided for multiplying a first and second binary number including adding a first exponent value associated with the first binary number to a second exponent value associated with the second binary number and multiplying a first mantissa value associated with the first binary number to a second mantissa value associated with the second binary number. The method includes performing the exponent adding and mantissa multiplying substantially in parallel. The method further includes performing at least one of adding or subtracting a third binary number to the product. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus.
    Type: Application
    Filed: August 12, 2015
    Publication date: December 3, 2015
    Inventor: Scott Hilker
  • Patent number: 9141337
    Abstract: A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bit-shifting circuit that is communicatively coupled to the first, second and third precision operation circuits. A method is also provided for multiplying a first and second binary number including adding a first exponent value associated with the first binary number to a second exponent value associated with the second binary number and multiplying a first mantissa value associated with the first binary number to a second mantissa value associated with the second binary number. The method includes performing the exponent adding and mantissa multiplying substantially in parallel. The method further includes performing at least one of adding or subtracting a third binary number to the product. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: September 22, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Scott Hilker
  • Patent number: 8838664
    Abstract: The disclosed embodiments relate to methods and apparatus for accurately, efficiently and quickly executing a fused multiply-and-accumulate instruction with respect to floating-point operands that have packed-single-precision format. The disclosed embodiments can speed up computation of a high-part of a result during a fused multiply-and-accumulate operation so that cycle delay can be reduced and so that power consumption can be reduced.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: September 16, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David Oliver, Debjit Dassarma, Hanbing Liu, Scott Hilker
  • Publication number: 20130282784
    Abstract: A device and methods are disclosed for communicating an unrounded result from one arithmetic calculation for use in a second, subsequent calculation. For example, an unrounded result of a first calculation can be forwarded to provide a multiplier, a multiplicand or an addend operand for the subsequent operation. The operand can be forwarded to the input of the same fused multiply addition module (FMAM) that supplied the result, or to another FMAM, and do so without regard to the precision of the forwarded operand, the precision of the subsequent operation, or the native precision of the FMAM.
    Type: Application
    Filed: June 19, 2013
    Publication date: October 24, 2013
    Inventors: David S. Oliver, Debjit Das Sarma, Scott Hilker
  • Patent number: 8495121
    Abstract: A device and methods are disclosed for communicating an unrounded result from one arithmetic calculation for use in a second, subsequent calculation. For example, an unrounded result of a first calculation can be forwarded to provide a multiplier, a multiplicand or an addend operand for the subsequent operation. The operand can be forwarded to the input of the same fused multiply addition module (FMAM) that supplied the result, or to another FMAM, and do so without regard to the precision of the forwarded operand, the precision of the subsequent operation, or the native precision of the FMAM.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: July 23, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David S. Oliver, Debjit Das Sarma, Scott Hilker
  • Patent number: 8407271
    Abstract: An apparatus and method for computing a rounded floating point number. A floating point unit (FPU) receives an instruction to round a floating point number to a nearest integral value and retrieves a binary source operand having an exponent of a fixed first number of bits and a mantissa of a fixed second number of bits. If the unbiased exponent value is greater than or equal to zero and less than the fixed second number, the FPU generates a mask having N consecutive ‘1’ bits beginning with the least significant bit and whose remaining bits have a value of ‘0’, where N is equal to the fixed second number minus the unbiased exponent value. The FPU computes a bitwise OR of the source operand with the mask, increments the result if the instruction is to round up, and computes a bitwise AND of the result with the inverse of the mask.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: March 26, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kevin Hurd, Daryl Lieu, Kelvin Goveas, Scott Hilker
  • Publication number: 20130060828
    Abstract: A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bit-shifting circuit that is communicatively coupled to the first, second and third precision operation circuits. A method is also provided for multiplying a first and second binary number including adding a first exponent value associated with the first binary number to a second exponent value associated with the second binary number and multiplying a first mantissa value associated with the first binary number to a second mantissa value associated with the second binary number. The method includes performing the exponent adding and mantissa multiplying substantially in parallel. The method further includes performing at least one of adding or subtracting a third binary number to the product. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus.
    Type: Application
    Filed: September 6, 2011
    Publication date: March 7, 2013
    Inventor: Scott Hilker
  • Publication number: 20130007075
    Abstract: The disclosed embodiments relate to methods and apparatus for accurately, efficiently and quickly executing a fused multiply-and-accumulate instruction with respect to floating-point operands that have packed-single-precision format. The disclosed embodiments can speed up computation of a high-part of a result during a fused multiply-and-accumulate operation so that cycle delay can be reduced and so that power consumption can be reduced.
    Type: Application
    Filed: June 29, 2011
    Publication date: January 3, 2013
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: David Oliver, Debjit Dassarma, Hanbing Liu, Scott Hilker
  • Publication number: 20120278591
    Abstract: A microprocessor is provided that has a datapath that is split into upper and lower portions. The microprocessor includes a centralized crossbar switch module having a single data movement module. The data movement module is capable of processing instructions that require operands to be exchanged between upper and lower 64-bit halves of the split architecture. The data movement module can access and process all instructions that require simultaneous access to the entire register contents of the upper and lower portions. The data movement module is configured to execute any one of a number of different instructions to perform data manipulation with respect to one or more “split-operands” (also referred to simply as “operands” herein). The data movement module can exchange data (bytes and/or bits) of operands for the upper and lower 64-bit halves so that bytes and/or bits of operands can be moved or rearranged to other positions during execution of a particular instruction.
    Type: Application
    Filed: April 27, 2011
    Publication date: November 1, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Scott HILKER, Kevin HURD, Mark GIBSON, Jonathan CHOY
  • Publication number: 20110055307
    Abstract: An apparatus and method for computing a rounded floating point number. A floating point unit (FPU) receives an instruction to round a floating point number to a nearest integral value and retrieves a binary source operand having an exponent of a fixed first number of bits and a mantissa of a fixed second number of bits. If the unbiased exponent value is greater than or equal to zero and less than the fixed second number, the FPU generates a mask having N consecutive ‘1’ bits beginning with the least significant bit and whose remaining bits have a value of ‘0’, where N is equal to the fixed second number minus the unbiased exponent value. The FPU computes a bitwise OR of the source operand with the mask, increments the result if the instruction is to round up, and computes a bitwise AND of the result with the inverse of the mask.
    Type: Application
    Filed: August 28, 2009
    Publication date: March 3, 2011
    Inventors: Kevin Hurd, Daryl Lieu, Kelvin Goveas, Scott Hilker
  • Publication number: 20100125620
    Abstract: A device and methods are disclosed for communicating an unrounded result from one arithmetic calculation for use in a second, subsequent calculation. For example, an unrounded result of a first calculation can be forwarded to provide a multiplier, a multiplicand or an addend operand for the subsequent operation. The operand can be forwarded to the input of the same fused multiply addition module (FMAM) that supplied the result, or to another FMAM, and do so without regard to the precision of the forwarded operand, the precision of the subsequent operation, or the native precision of the FMAM.
    Type: Application
    Filed: November 20, 2008
    Publication date: May 20, 2010
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: David S. Oliver, Debjit Das Sarma, Scott Hilker
  • Publication number: 20100125621
    Abstract: An arithmetic processing unit is disclosed that can perform multiply operations, addition operations, or a combination thereof. The arithmetic processing unit can operate in two modes. The first mode supports one single, double, or extended-precision computation, and the second mode supports two simultaneous single-precision computations using the same exponent and mantissa datapaths.
    Type: Application
    Filed: November 20, 2008
    Publication date: May 20, 2010
    Applicant: Advanced Micro Devices, Inc.
    Inventors: David S. Oliver, Debjit Das Sarma, Scott Hilker