Abstract: A system grants “provisional privileges” to a user request for the purpose of provisionally performing a requested transaction. If the provisionally-performed transaction does not put the system in a degraded state, the transaction is authorized despite the user request having inadequate privileges originally.

Abstract: A software license includes conditional policies that define usage rights for software. A conditional policy contains a condition. If the condition is met, software is authorized for use in accordance with the conditional policy. Conditional policies can authorize software use in accordance with predetermined usage rights defined in the conditional policy. Conditional policies also can authorize software use as defined by plug-in computer programs provided by an independent software vendor. For example, a conditional policy can define the number of processors that can concurrently execute a software product dependent upon the type of CPU in the processor. Or, the maximum number of processors that can concurrently execute a software product can be defined in a plug-in that is called by a software license manager application, or the like.

Abstract: A flexible use licensing system for an application comprising a plurality of licensable products is provided comprising an application level product policy definition license, and a licensable product policy definition license corresponding to each licensable product. The flexible use license further comprises a rights account certificate for validating the use license against a variety of environmental conditions, and an external validation component for validating the use license at a licensing authority without the transmittal of the entire use license.

Abstract: A method of forming a flash memory with a protruded floating gate. A substrate is provided. An isolation area and a plurality of patterned conductive layers are sequentially formed on the substrate. The isolation area protrudes from the upper surface of the substrate to isolate the patterned conductive layers. A photo resist layer is formed on the patterned conductive layer. The present invention also provides a flash memory with a protruded floating gate comprised a substrate, a plurality of protruded floating gates, an insulator, and a control gate.

Abstract: A method of forming a flash memory with a protruded floating gate. A substrate is provided. An isolation area and a plurality of patterned conductive layers are sequentially formed on the substrate. The isolation area protrudes from the upper surface of the substrate to isolate the patterned conductive layers. A photo resist layer is formed on the patterned conductive layer. The present invention also provides a flash memory with a protruded floating gate comprised a substrate, a plurality of protruded floating gates, an insulator, and a control gate.

Abstract: A method of forming a flash memory with a protruded floating gate. A substrate is provided. An isolation area and a plurality of patterned conductive layers are sequentially formed on the substrate. The isolation area protrudes from the upper surface of the substrate to isolate the patterned conductive layers. A photo resist layer is formed on the patterned conductive layer. The present invention also provides a flash memory with a protruded floating gate comprised a substrate, a plurality of protruded floating gates, an insulator, and a control gate.

Abstract: A method of forming a flash memory with a protruded floating gate. A substrate is provided. An isolation area and a plurality of patterned conductive layers are sequentially formed on the substrate. The isolation area protrudes from the upper surface of the substrate to isolate the patterned conductive layers. A photo resist layer is formed on the patterned conductive layer. The present invention also provides a flash memory with a protruded floating gate comprised a substrate, a plurality of protruded floating gates, an insulator, and a control gate.

Abstract: A novel flash memory structure is disclosed, which includes a tunnel oxide layer on a semiconductor substrate, an array of gate electrode stacks formed on the tunnel oxide layer, and alternating source/drain regions formed between the stacks. A first dielectric layer is formed over the stacks and the substrate with a source line opening down to the source regions. A source line is formed above the source regions, partially filling the source line opening. The source line is located between the gate electrode stacks and has a surface level below a top surface of the stacks. A second dielectric layer is formed over the source line and the first dielectric layer with a plug opening down to the drain regions. A drain metal plug is formed over the drain regions, filling the plug opening. A metal bit line is formed over the second dielectric layer contacting the drain metal plug.

Abstract: A novel flash memory structure is disclosed, which includes a tunnel oxide layer on a semiconductor substrate, an array of gate electrode stacks formed on the tunnel oxide layer, and alternating source/drain regions formed between the stacks. A first dielectric layer is formed over the stacks and the substrate with a source line opening down to the source regions. A source line is formed above the source regions, partially filling the source line opening. The source line is located between the gate electrode stacks and has a surface level below a top surface of the stacks. A second dielectric layer is formed over the source line and the first dielectric layer with a plug opening down to the drain regions. A drain metal plug is formed over the drain regions, filling the plug opening. A metal bit line is formed over the second dielectric layer contacting the drain metal plug.