Abstract: An end effector cleaner for removing excess sealant from an end effector is provided. The end effector cleaner includes a first spool, a second spool, a medium for removing excess sealant from the end effector, a support member configured to support a portion of the medium, a motor for rotating the second spool, an advancement sensor for detecting a presence of the end effector and sending a signal for rotating the motor, and a roll sensor for detecting a dimension of the medium wound on at least one of the first spool and the second spool. One end of the medium is wound on the first spool and the other end of the medium is wound on the second spool, and the portion of the medium is positioned to receive excess sealant of the end effector.

Abstract: An end effector cleaner for removing excess sealant from an end effector is provided. The end effector cleaner includes a first spool, a second spool, a medium for removing excess sealant from the end effector, a support member configured to support a portion of the medium, a motor for rotating the second spool, an advancement sensor for detecting a presence of the end effector and sending a signal for rotating the motor, and a roll sensor for detecting a dimension of the medium wound on at least one of the first spool and the second spool. One end of the medium is wound on the first spool and the other end of the medium is wound on the second spool, and the portion of the medium is positioned to receive excess sealant of the end effector.

Abstract: A method and apparatus for performing bi-endian byte and short accesses in a single endian microprocessor. The present invention is used in a microprocessor or in a microprocessor in a computer system. The present invention provides a single endian microprocessor that promotes sub-word accesses to word accesses with a means for manipulating the two least significant bits of the access address to point to the correct sub-word data returned during an access to bi-endian external memory. The method for manipulating the address bits is also used to allow a single endian data cache to operate with the bi-endian external memory. The two LSBs of the address are manipulated such that the pointer values are A1# and A0# for word promoted byte accesses or cacheable accesses. For word promoted short accesses or cacheable accesses, the pointer values are A1# and A0. The present invention offers increased flexibility in interfacing a single-endian microprocessor with bi-endian systems.

Abstract: A hierarchical memory which includes a backing store read/write memory (18) for storing first words, and a read-only memory RAM (60) for storing frequently used words. The buffer store has two parts, a cache RAM (64) and a two-word queue (62) comprised of two fetch buffers. The cache RAM is provided for storing a copy of some of the word stored in the backing store in accordance with a use algorithm. The ROM, queue buffers and cache RAM are simultaneously searched to see if the address for requested words is in either of them. If not, a fetch (76) is made of the backing store (18) and the words are written into the fetch buffers. The next time that address is presented, the fetch buffers are written into the cache and simultaneously read out to the bus. A first Y-mux (63) is provided between the ROM and the cache RAM for multiplexing the appropriate ROM columns to drive the Cache RAM bit lines directly when an internal micro-address is selected.