Abstract: In one aspect, a system for detecting and addressing an unsafe working condition may include a work vehicle structured to operate over a work surface. The system can also include a proximity sensor mounted to the work vehicle and structured to generate a proximity sensor signal indicative of a presence of an obstacle within a dynamic zone of operation of the work vehicle. The system may also include a safety control system configured to receive the proximity sensor signal and execute a safety action based upon the proximity sensor signal, wherein the safety system is further configured to adjust the dynamic zone of operation based upon an object detection confidence measure.

Abstract: A mini C-arm with a movable X-ray source is disclosed. The mini C-arm including a moveable base, a C-arm assembly, and an arm assembly for coupling the C-arm assembly and the base. The C-arm assembly includes a first end, a second end, and a curved intermediate body portion defining an arc length. The source is positioned adjacent to the first end. A detector is positioned at the second end. The source is moveable along the arc length and relative to the detector to enable a plurality of images of the patient's anatomy to be acquired including a first image when the X-ray source is at a first position and a second image when the X-ray source is at a second position. The images being taken without moving the patient's anatomy. The C-arm assembly may include a motor and a belt drive system for moving the source relative to the detector.

Abstract: Disclosed is a circuit comprising an inverter circuit which comprises inverters and level shifters; and a modulation circuit comprising a pull-up circuit and a pull-down circuit, the modulation circuit coupled to the inverter circuit to regulate the response of the circuit to an input voltage for various power supply voltage levels by the pull-up or pull-down circuit. Other embodiments are also disclosed.

Abstract: A variable impedance sense (VIS) circuit (600) can detect and store an input offset value inherent in a sensing loop (620 and/or 622). According to a detected input offset polarity, a resulting impedance matching binary code can be adjusted to compensate for error that can be introduced by the input offset. The binary code can also be adjusted to compensate for additional error that can be introduced by dropping a least significant bit (LSB) of the code to reduce noise effects caused by the switching of the LSB.

Abstract: An apparatus comprising a distributed multiplexer configured to receive a distributed input group of signals. The distributed multiplexer may be configured to evenly load the distributed input groups.

Abstract: A data path (200) can be configured to accommodate different clocking arrangements. In one mode, data values may be output at a single data rate: one data value every clock cycle. In another mode, data values may be output at a double data rate: two data values every clock cycle. A data path (200) can be compact circuit structure, needing only an additional mode multiplexer (206) and inverter over a conventional D-type master-slave flip-flop.

Abstract: A multi-port memory cell (200) can be formed from seven transistors. Single ended write operations can be performed without a boosted word line voltage or variable power supply. A data value (D/DB) stored in the memory cell (200) can be cleared by shorting complementary data nodes (204-0 and 204-1) together. Write data can then be placed on a bit line. Complementary data nodes (204-0 and 204-1) can then be isolated once again, resulting in the write data being latched within the memory cell (300). An access method (700) for a multi-port memory cell is also described.

Abstract: A method and system for automatically building a bit order data structure of configuration bits for a programmable logic device. One embodiment of the present invention first identifies a plurality of memory cells in a hierarchical schematic representation of the programmable device. Next, this embodiment determines a plurality of addresses corresponding to the plurality of memory cells. This embodiment next determines a plurality of logical names for the plurality of memory cells. Then, based on an order in which the plurality of addresses are to be loaded into the programmable logic device, this embodiment orders the plurality of logical names for the plurality of memory cells. Another embodiment first accesses a database comprising a plurality of logical names corresponding to a plurality of addresses. Then, this embodiment accesses a database specifying an order in which the plurality of addresses are to be loaded into the programmable logic device.

Abstract: An apparatus comprising an input section and an output section. The input section may be configured to generate a first control signal and a second control signal in response to an input signal and a select signal. The output section may be configured to generate an output signal in response to the first and second control signals. The output signal may be (i) related to the input signal when in a first mode and (ii) disabled when in a second mode.

Abstract: A buffer includes a pull-up level shifter coupled to an input signal. A pull-down level shifter separate from the pull-up level shifter is coupled to the input signal. A driver is coupled to the pull-up level shifter and the pull-down level shifter.

Abstract: An input buffer system has an input clipping circuit. The input clipping circuit has a high voltage input and uses transistors all being the thin oxide type transistors. A high voltage detect circuit is coupled to the input clipping circuit. An input buffer circuit is coupled to the input clipping circuit and has a low voltage output range.

Abstract: An input buffer circuit has a pass gate circuit coupled to an input. A pseudo-differential amplifier is coupled to the pass gate circuit. A level shifter is coupled to the pseudo-differential amplifier.

Abstract: An apparatus comprising a first stage and a second stage. The first stage may comprise a first section and a second section. The second stage may be embedded between the first and second sections. The first and second stages may be configured to equalize signal paths between a plurality of inputs of the first stage and a plurality of outputs of the second stage.

Abstract: The present invention relates to surgical retractors and devices for stabilizing a predetermined area of the body during a surgical procedure, more particularly to surgical retractors and stabilizing devices used in connection with minimally invasive coronary artery bypass grafting surgical procedures, and more specifically to surgical retractors and stabilizing devices especially configured for use with each other for such surgical procedures wherein the retractor includes an external rail system which enables the surgeon to position a stabilization arm having first and second shaft segments on either of the arms or the rack segment of the retractor and also includes a connector which is spaced apart from the sled member and stabilization device to releasably control the movement and rotation of the stabilization device with respect to the stabilization arm and the rotation of the stabilization arm with respect to the retractor actuation of a single knob or actuator.

Abstract: A segmented arm support system and method for attachment to a surgical retractor includes an arm having a plurality of segments which can be joined together in frictional, locking engagement. In an unlocked state, the flexible arm can be manually positioned and the stabilization device placed over a localized area of tissue. Upon tightening of a cable running through the segments, the segments are brought together in frictional engagement. Each segment has a convex outer wall and a concave inner surface for attachment to adjacent segments. The segments are constructed of a stainless steel substrate material and coated with a high friction plating material to permit frictional engagement of the segments, thereby allowing for adequate tightening and locking of the arm.

Abstract: An apparatus comprising a first compare circuit, a second compare circuit and a memory. The first compare circuit may be configured to present a first match signal in response to a first address and a second address. The second compare circuit may be configured to present a second match signal in response to the first match signal, a first write enable signal and a second write enable signal. The memory may also be configured to present the first and second write enable signals. In one example, the memory may be configured to store and retrieve data with zero waiting cycles in response to the second match signal.

Abstract: A method and system for automatically identifying configuration cell addresses in a schematic hierarchy is disclosed. In one embodiment of the present invention, a memory cell (e.g., a configuration bit) is identified in a schematic hierarchy. Next, this embodiment determines an address for the memory cell. Then, this embodiment determines a unique name for the memory cell. The name is comprised of a hierarchical logical name and a schematic path name. By traversing the schematic and using logical names, all addresses of configuration bits of a circuit design may be automatically determined. The process is repeated for each memory cell in the schematic. This embodiment stores the unique name of the configuration bit and the address of the configuration bit in a data structure.

Abstract: An apparatus comprising a native device coupled to an input of an amplifier. The native device is configured to provide a high voltage protection in response to an enable signal.