Abstract: A system and method is disclosed which integrates a machine learning solution into a large scale, distributed transaction processing system using a supporting architecture comprising a combination of computer hardware and software. Methods of using a system comprising such supporting architecture provide application designers access to the functionality included in a machine learning solution, but might also provide additional functionality not supported by the machine learning solution itself.

Abstract: There is disclosed a system and method for creating value by facilitating third party participation in mobile commerce transactions, providing consumers with a unified perspective of commercial activity, and selectively implementing discounts. The system may include a computerized engine and a point of sale wallet, which may be embedded in a personal trusted device. The computerized engine may be programmed to selectively implement a discount associated with a particular transaction. The personal trusted device may comprise a wireless communications technology, which enables the device to communicate with a back-end system and/or other point of sale devices. The personal trusted device may serve as the nexus of consumer transactions by facilitating payment as well as receipt and storage of electronic receipts. The personal trusted device may also be configured to transmit electronic receipts via the communications technology.

Abstract: The present disclosure is generally directed to a method and apparatus to communicate data between two or more semiconductor devices. In an embodiment, a method includes synchronizing a master device with a slave device, where the master device includes a semiconductor device. Synchronizing includes transmitting a first synchronization marker data pattern via a first serial interface from the master device at a first time, and receiving a second synchronization marker data pattern via a second serial interface at the master device at a second time in response to transmitting the first synchronization marker data pattern. Synchronizing also includes determining, based at least in part on the first time and the second time, a third time when a reply is to be received by the master device in response to a request transmitted from the master device to the slave device.

Abstract: The present disclosure is generally directed to a method of communicating data between two or more semiconductor devices. Serial interfaces using the method have a reduction in latency compared to conventional serial interfaces. The method enables features needed for a serial interface, such as limited run lengths and recognizable data boundaries to establish alignment. In addition, a method for synchronizing two or more semiconductor devices through serial interfaces has been presented. This is done by passing a marker data pattern through the system.

Abstract: Resource allocation in a contact center can be performed using a network of nodes. Such a network of nodes can be organized according into resource nodes, domain nodes, and service nodes, with paths from the domain nodes, through the service nodes, to the resource nodes being used in the allocation.

Abstract: A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. A transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.

Abstract: A programmable logic device includes a plurality of programmable multi-gigabit transceivers, programmable logic fabric, and a control module. Each of the plurality of programmable multi-gigabit transceivers is individually programmed to a desired transceiving mode of operation in accordance with a plurality of transceiver settings. The programmable logic fabric is operably coupled to the plurality of programmable multi-gigabit transceivers and is configured to process at least a portion of the data being transceived via the multi-gigabit transceivers. The control module is operably coupled to produce the plurality of transceiver settings based on a desired mode of operation for the programmable logic device.

Abstract: A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. A transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.

Abstract: A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. A transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.

Abstract: There is disclosed a system and method for creating value by facilitating third party participation in mobile commerce transactions, providing consumers with a unified perspective of commercial activity, and selectively implementing discounts. The system may include a computerized engine and a point of sale wallet, which may be embedded in a personal trusted device. The computerized engine may be programmed to selectively implement a discount associated with a particular transaction. The personal trusted device may comprise a wireless communications technology, which enables the device to communicate with a back-end system and/or other point of sale devices. The personal trusted device may serve as the nexus of consumer transactions by facilitating payment as well as receipt and storage of electronic receipts. The personal trusted device may also be configured to transmit electronic receipts via the communications technology.

Abstract: Method and apparatus for configuring a programmable logic device to perform testing on a signal channel is described. Configurable logic of the programmable logic device is configured for a test mode. Configurable interconnects are configured for communication from or to the configurable logic to or from transceivers coupled to the configurable input/output interconnect to communicate test signals.

Abstract: A memory device and system are disclosed that may include a serial data interface, a serial address interface, and a reference clock interface. The reference clock interface is configured to receive a signal from a reference clock source that provides a reference clock signal to a memory control device. The serial interfaces are coupled to other memory devices or memory control devices. A method of transferring data within a memory system using serial interfaces is also disclosed. The method includes performing clock multiplication on a reference clock to provide a multiplied clock, using the multiplied clock to serialize and transmit data onto a serial interface, recovering data from the seal interface, using the reference clock to determine an initial frequency for use by clock and data recovery module, using the data recovered from the serial interface to determine a phase and final frequency of a recovered clock, and using the recovered clock to de-serialize received serial data into parallel data words.

Abstract: The present disclosure is generally directed to a method of communicating data between two or more semiconductor devices. Serial interfaces using the method have a reduction in latency compared to conventional serial interfaces. The method enables features needed for a serial interface, such as limited run lengths and recognizable data boundaries to establish alignment. In addition, a method for synchronizing two or more semiconductor devices through serial interfaces has been presented. This is done by passing a marker data pattern through the system.

Abstract: A memory device and system are disclosed that may include a serial data interface, a serial address interface, and a reference clock interface. The reference clock interface is configured to receive a signal from a reference clock source that provides a reference clock signal to a memory control device. The serial interfaces are coupled to other memory devices or memory control devices. A method of transferring data within a memory system using serial interfaces is also disclosed. The method includes performing clock multiplication on a reference clock to provide a multiplied clock, using the multiplied clock to serialize and transmit data onto a serial interface, recovering data from the seal interface, using the reference clock to determine an initial frequency for use by clock and data recovery module, using the data recovered from the serial interface to determine a phase and final frequency of a recovered clock, and using the recovered clock to de-serialize received serial data into parallel data words.

Abstract: Method and apparatus for auto-negotiation of a programmable logic device for any of a plurality of communication protocols is described. The programmable logic device is programmed for auto negotiation to establish a communication session. The programmable logic device has access to transceiver attributes. A portion of the transceiver attributes are selected in response to session information from the auto negotiation. The portion of the transceiver attributes selected are for configuring at least one transceiver for a communication protocol.

Abstract: A system is disclosed for a digital rights management system which enforces license rights by establishing an account domain of registered consumer devices which may each receive a decryption key to be used to decode digital content bought by any of the devices within the account domain. Such system further enables the decentralization of content sharing by establishing a network of trusted intermediate devices to manage licenses on end devices for a central rights provider.

Abstract: A method and system is disclosed herein for decoupling billing for web services from the application logic which governs those web services by instrumenting a web services stack to monitor SOAP envelopes for pre-determined elements and to use those elements to determine questions as to authorization for solvency as well as calculate charges for said web services.

Abstract: A programmable logic device includes a plurality of programmable multi-gigabit transceivers, programmable logic fabric, and a control module. Each of the plurality of programmable multi-gigabit transceivers is individually programmed to a desired transceiving mode of operation in accordance with a plurality of transceiver settings. The programmable logic fabric is operably coupled to the plurality of programmable multi-gigabit transceivers and is configured to process at least a portion of the data being transceived via the multi-gigabit transceivers. The control module is operably coupled to produce the plurality of transceiver settings based on a desired mode of operation for the programmable logic device.

Abstract: A system is disclosed for a digital rights management system which enforces license rights by incorporating a decryption key in a license rights package that further includes an account number associated with a primary consumer. The digital rights management system also includes a mechanism for renewing/updating the license by charging the account number associated with a primary consumer. This way, the consumer may transfer the license rights package along with the digital content to any personal devices he likes but he is discouraged from freely disseminating the license package as uses by other consumers will be debited against his package or, if renewed/extended, charged against his account.

Abstract: There is disclosed a simplified rating language for crafting price plans for ratable events which may be interpreted by either a source level interpreter resident upon a device also comprising a device based rating engine or via a virtual machine designed for said rating language.