Patents by Inventor Scott J. Derner

Scott J. Derner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210272958
    Abstract: Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.
    Type: Application
    Filed: May 19, 2021
    Publication date: September 2, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Publication number: 20210271377
    Abstract: Computer-readable media and methods for a geospatial image map are disclosed. A computer-readable medium has computer-readable instructions stored thereon. The computer-readable instructions are configured to instruct one or more processors to display a map of a selected geographic region on an electronic display. The map includes geographic sub-regions displayed within the map. The computer-readable instructions are configured to instruct the one or more processors to select discrete images corresponding to the geographic sub-regions, and display the discrete images at the same time on the electronic display as an overlay to the map. A method includes displaying a map of a selected geographic region, displaying geographic sub-regions of the selected geographic region, selecting discrete images corresponding to the geographic sub-regions and one or more selected categories, and displaying the discrete images simultaneously on the electronic display as an overlay to the map.
    Type: Application
    Filed: May 20, 2021
    Publication date: September 2, 2021
    Inventors: Scott J. Derner, Patrick Mullarkey
  • Patent number: 11107515
    Abstract: Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Christopher J. Kawamura
  • Patent number: 11094697
    Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Gloria Yang, Suraj J. Mathew, Raghunath Singanamalla, Vinay Nair, Scott J. Derner, Michael Amiel Shore, Brent Keeth, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
  • Publication number: 20210249416
    Abstract: Some embodiments include an integrated assembly having first conductive lines which extend along a first direction, and having second conductive lines over the first conductive lines and which extend along a second direction that crosses the first direction. Capacitors are over the second conductive lines. The second conductive lines are operatively proximate active structures to gatedly couple a first set of the capacitors to the first conductive lines through the active structures. Shield structures are between the first conductive lines and extend along the first direction. A voltage source is electrically coupled to the shield structures through a second set of the capacitors. Some embodiments include assemblies having two or more decks stacked one atop another.
    Type: Application
    Filed: February 10, 2020
    Publication date: August 12, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Jiyun Li, Scott J. Derner
  • Patent number: 11069385
    Abstract: Some embodiments include an integrated assembly having a second deck over a first deck. A first true digit line has first and second segments along the first deck. A first complementary digit line has third and fourth segments along the second deck. The first true digit line is comparatively compared to the first complementary digit line. A second true digit line has a third region along the first deck and a fourth region along the second deck. The third region is adjacent the first segment, and the fourth region is adjacent the third segment. A second complementary digit line has a fifth region along the first deck and has a sixth region along the second deck. The fifth region is adjacent the second segment, and the sixth region is adjacent the fourth segment. The second true digit line is comparatively compared to the second complementary digit line.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: July 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jiyun Li, Scott J. Derner
  • Patent number: 11062753
    Abstract: Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: July 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Charles L. Ingalls, Scott J. Derner
  • Publication number: 20210183428
    Abstract: Some embodiments include an integrated memory assembly having a first memory array deck over a second memory array deck. A first series of conductive lines extends across the first memory array deck, and a second series of conductive lines extends across the second memory array deck. A first conductive line of the first series and a first conductive line of the second series are coupled with a first component through a first conductive path. A second conductive line of the first series and a second conductive line of the second series are coupled with a second component through a second conductive path. The first and second conductive lines of the first series extend through first isolation circuitry to the first and second conductive paths, respectively; and the first and second conductive lines of the second series extend through second isolation circuitry to the first and second conductive paths, respectively.
    Type: Application
    Filed: February 9, 2021
    Publication date: June 17, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Patent number: 11031400
    Abstract: Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Patent number: 11023111
    Abstract: A system, apparatuses such as a non-transitory readable medium, and a method for generating a geospatial interactive composite web-based image map are disclosed. The system may be configured to receive, from a user device, a request for creating a geospatial interactive composite web-based image map for a selected region of map data displayed by the user device, select images responsive to the request corresponding to defined sub-regions within the selected region of the map data displayed by the user device, construct a collage for the geospatial composite web-based image map responsive to selecting the images, and transmit the collage to the user device for display thereon as an overlay to the map data.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: June 1, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Patrick Mullarkey
  • Publication number: 20210143142
    Abstract: Some embodiments include an integrated assembly having a base comprising sense-amplifier-circuitry, a first deck over the base, and a second deck over the first deck. The first deck includes a first portion of a first array of first memory cells, and includes a first portion of a second array of second memory cells. The second deck includes a second portion of the first array of the first memory cells, and includes a second portion of the second array of the second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry.
    Type: Application
    Filed: December 17, 2020
    Publication date: May 13, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Hiroki Fujisawa, Charles L. Ingalls, Richard J. Hill, Gurtej S. Sandhu, Scott J. Derner
  • Patent number: 10998031
    Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven to the first voltage responsive to the voltage of the first node being less than the second node.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Christopher J. Kawamura, Scott J. Derner
  • Patent number: 10998027
    Abstract: Some memory circuitry comprises a stack of multiple tiers individually comprising memory cells individually comprising an elevationally-extending transistor. The tiers individually comprise multiple access lines that individually electrically couple together a row of the memory cells in that individual tier. The tiers individually comprise access-line-driver circuitry comprising an elevationally-extending transistor.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls, Tae H. Kim
  • Publication number: 20210125661
    Abstract: In the examples disclosed herein, a memory array can have a first group of memory cells coupled to a first digit line at a first level and a second group of memory cells coupled to a second digit line at the first level. A third digit line can be at a second level and can be coupled to a main sense amplifier. A first vertical thin film transistor (TFT) can be at a third level between the first and second levels can be coupled between the first digit line and the third digit line. A second vertical TFT can be at the third level and can be coupled between the second digit line and the third digit line. A local sense amplifier can be coupled to the first and second digit lines.
    Type: Application
    Filed: January 4, 2021
    Publication date: April 29, 2021
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Patent number: 10957681
    Abstract: Some embodiments include an integrated assembly having a base comprising sense-amplifier-circuitry, a first deck over the base, and a second deck over the first deck. The first deck includes a first portion of a first array of first memory cells, and includes a first portion of a second array of second memory cells. The second deck includes a second portion of the first array of the first memory cells, and includes a second portion of the second array of the second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hiroki Fujisawa, Charles L. Ingalls, Richard J. Hill, Gurtej S. Sandhu, Scott J. Derner
  • Patent number: 10957382
    Abstract: Some embodiments include an integrated assembly having a base with sense-amplifier-circuitry. A first deck is over the base, and includes a first array of first memory cells. A second deck over the first deck, and includes a second array of second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Publication number: 20210074714
    Abstract: Some embodiments include an integrated assembly. The integrated assembly has a first transistor with a horizontally-extending channel region between a first source/drain region and a second source/drain region; has a second transistor with a vertically-extending channel region between a third source/drain region and a fourth source/drain region; and has a capacitor between the first and second transistors. The capacitor has a first electrode, a second electrode, and an insulative material between the first and second electrodes. The first electrode is electrically connected with the first source/drain region, and the second electrode is electrically connected with the third source/drain region. A digit line is electrically connected with the second source/drain region. A conductive structure is electrically connected with the fourth source/drain region.
    Type: Application
    Filed: October 28, 2020
    Publication date: March 11, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Publication number: 20210074357
    Abstract: Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells are disclosed. The apparatus includes a first memory cell including first and second ferroelectric capacitors configured to store charges representing complementary logical values, a second memory cell including first and second dielectric capacitors configured to store charges representing complementary logical values, a first bit line selectably coupled to the first ferroelectric capacitor of the first memory cell and to the first dielectric capacitor of the second memory cell, a second bit line selectably coupled to the second ferroelectric capacitor of the first memory cell and to the second dielectric capacitor of the second memory cell, and a sense amplifier coupled to the first and second bit lines.
    Type: Application
    Filed: November 19, 2020
    Publication date: March 11, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Scott J. Derner, Michael A. Shore
  • Publication number: 20210074345
    Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.
    Type: Application
    Filed: November 19, 2020
    Publication date: March 11, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: SCOTT J. DERNER, CHRISTOPHER J. KAWAMURA
  • Patent number: 10943642
    Abstract: Some embodiments include an integrated memory assembly having a first memory array deck over a second memory array deck. A first series of conductive lines extends across the first memory array deck, and a second series of conductive lines extends across the second memory array deck. A first conductive line of the first series and a first conductive line of the second series are coupled with a first component through a first conductive path. A second conductive line of the first series and a second conductive line of the second series are coupled with a second component through a second conductive path. The first and second conductive lines of the first series extend through first isolation circuitry to the first and second conductive paths, respectively; and the first and second conductive lines of the second series extend through second isolation circuitry to the first and second conductive paths, respectively.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls