Abstract: A circuit for detecting manufacturing deficiencies in semi-conductor devices and selecting marketable chips comprises a speed circuit to determine the speed at which a particular chip operates. The speed circuit is a small, self-contained circuit that may be placed on any type of semi-conductor chip. It includes an oscillator, a counter, and a control logic circuit. The speed circuit is coupled to an external clock and a control processor. The external clock provides a benchmark against which the operation of the chip can be compared. The control processor uses the output of the speed circuit to compute the speed at which the semi-conductor device operates.

Abstract: A multi-input logic gate is disclosed having particular application for use as an AND or OR gate in a digital circuit. The OR gate of the present invention includes drive, sense and reference rails. A plurality of input lines are coupled to a gate of a plurality of N-channel transfers disposed between the drive and sense rails, one input line per transistor. The drive rail is coupled to ground through an N-channel transistor whose gate is controlled by the state of a detect line. The sense and reference rails are coupled to a voltage source (V.sub.dd) through P-channel transistors whose gate is also coupled to the detect line. The P-channel transistor coupled to the sense rail is sized to pass more current than the corresponding transfer on the reference rail. A sense amplifier is coupled to the sense and reference rails, and outputs a predetermined signal as a function of the voltage difference of the rails.