Abstract: One embodiment provides a method, the method including: detecting, using a content focus system, an attentive state of a user with respect to a display; determining, using the content focus system, the attentive state corresponds to content displayed on the display; and increasing, using the content focus system, a size of the content, wherein the increasing comprises increasing the content to a size that covers other content displayed on the display. Other aspects are described and claimed.

Abstract: One embodiment provides a method, the method including: detecting, at an information handling device utilizing a input detection system and while the information handling device is in a low power state, a physical user input at an input mechanism of the information handling device, wherein the detecting comprises detecting a force at the input mechanism; determining, utilizing the input detection system, the physical user input comprises a request to power-on the information handling device; and powering on the information handling device. Other aspects are claimed and described.

Abstract: For categorizing encrypted data files, a processor determines a block cipher key length for a data file based on data file contents. The processor encrypts the data file with an encryption cipher using the block cipher key length. The processor further determines a data type for the encrypted data file from macroscopic artifacts of the encrypted data file.

Abstract: Methods, systems, apparatus, and computer program products that can automatically answer communication sessions received from trusted callers are disclosed herein. One method includes maintaining, by a processor of an information handling device, a list of trusted callers encoded in a memory and automatically answering a communication session received by the information handling device from a trusted caller in the encoded list of trusted callers without receiving input from a user of the information handling device accepting the communication session on the information handling device. Systems, apparatus, and computer program products that include hardware and/or software that can perform the methods for automatically answering communication sessions received from trusted callers are also disclosed herein.

Abstract: A system for providing features at launch to an application. The system may execute a user-space launcher application. To execute the launcher application, the computing system may: wrap a process creation function with a process creation wrapper function, preload a function library comprising the process creation function, launch an application specified to the launcher application, intercept a call to the process creation function of the launched application with the process creation wrapper function, create a process on behalf of the launched application using the process creation function, and provide a feature at launch to the process of the launched application based on a parameter specified to the launcher.

Abstract: A system for providing features at launch to an application. The system may execute a user-space launcher application. To execute the launcher application, the computing system may: wrap a process creation function with a process creation wrapper function, preload a function library comprising the process creation function, launch an application specified to the launcher application, intercept a call to the process creation function of the launched application with the process creation wrapper function, create a process on behalf of the launched application using the process creation function, and provide a feature at launch to the process of the launched application based on a parameter specified to the launcher.

Abstract: An operating system provides instructions for execution by plural hardware threads of a multithreaded core of a processor, the plural hardware threads appearing as separate logical processors to the operating system. An abstraction layer converts respective identifiers of the plural hardware threads to a core identifier representing the core. The abstraction layer presents the core identifier to a user application to hide the plural hardware threads from the user application, and to present the core as a single-threaded core to the user application.

Abstract: An operating system provides instructions for execution by plural hardware threads of a multithreaded core of a processor, the plural hardware threads appearing as separate logical processors to the operating system. An abstraction layer converts respective identifiers of the plural hardware threads to a core identifier representing the core. The abstraction layer presents the core identifier to a user application to hide the plural hardware threads from the user application, and to present the core as a single-threaded core to the user application.

Abstract: In an embodiment of the invention, an apparatus and method to abstract a multithreaded processor core to single threaded processor core include performing the steps of: viewing, by an operating system, a first hardware thread and a second hardware thread in a processor core; and viewing, by a user application, the first hardware thread and the second hardware thread as a single CPU object.

Abstract: An embodiment of the invention provides an apparatus and method for accurate measurement of utilizations in a hardware multithreaded processor core. The apparatus and method perform the acts including: determining idle time spent cycles which are cycles that are spent in idle by a hardware thread in a processor core; determining idle consumed cycles which are cycles that are consumed in the idle time spent cycles, by the hardware thread; and determining at least one of a processor core utilization and a logical processor utilization based upon at least one of the idle time spent cycles (d1) and idle consumed cycles (d3).

Abstract: A determination of processor core utilization by a plurality of hardware threads over a time interval is made through a division of a length of the time interval by a total count of the plurality of hardware threads.

Abstract: An arrangement, in a computer system, for coordinating scheduling of threads on a plurality of processor sets (PSETs). The arrangement includes a first processor set (PSET) having a first set of scheduling resources, the first set of scheduling resources. The arrangement further includes a second processor set (PSET) having a second set of scheduling resources. The first set of scheduling resources is configured to schedule threads assigned to the first PSET only among processors of the first PSET, and the second set of scheduling resources is configured to schedule threads assigned to the second PSET only among processors of the second PSET.

Abstract: A method in a computer system for coordinating scheduling of threads among a plurality of processors. The method includes collecting, using a cooperative scheduling component (CSC), system data pertaining to the plurality of processors. The method further includes calculating, using the CSC, unified scheduling-related parameters (USRPs) from the system data. The method additionally includes furnishing the USRPs from the CSC to at least two of a thread launcher, a thread balancer, and a thread stealer, whereby at least two of the thread launcher, the thread balancer, and the thread stealer employ the USRPs to perform their respective scheduling-related tasks.

Abstract: In an embodiment of the invention, a method for dynamic hardware multithreading, includes: using a hardware halt function or a hardware yield function in a processor core in order to enable or disable a hardware thread that shares the core; wherein the hardware thread is disabled by placing the hardware thread in a halt state or yield state, and allowing another hardware thread to utilize the core.

Abstract: A computer-implemented method for traversing a first set of objects in a first dynamic list in a computer system. The method includes partitioning copies of the first set of objects into a plurality of second dynamic lists, each of the plurality of second dynamic lists being configured to contain a subset of the copies of the first set of objects, copies of the first set of objects being disposed in the plurality of second dynamic lists. The method also includes traversing the plurality of second dynamic lists using a plurality of traversal threads, thereby causing at least some of the copies of the first set of objects to be traversed in parallel.

Abstract: An embodiment of the invention provides an apparatus and method for accurate measurement of utilizations in a hardware multithreaded processor core. The apparatus and method perform the acts including: determining idle time spent cycles which are cycles that are spent in idle by a hardware thread in a processor core; determining idle consumed cycles which are cycles that are consumed in the idle time spent cycles, by the hardware thread; and determining at least one of a processor core utilization and a logical processor utilization based upon at least one of the idle time spent cycles (d1) and idle consumed cycles (d3).

Abstract: An embodiment of the invention provides an apparatus and method for fair share scheduling with hardware multithreading. The apparatus and method include the acts of: executing, by a first hardware thread in a processor core, a first software thread belonging to a fair share group; and permitting a second hardware thread in the processor core to execute a second software thread if that second software thread belongs to the fair share group.

Abstract: In an embodiment of the invention, an apparatus and method to abstract a multithreaded processor core to single threaded processor core include performing the steps of: viewing, by an operating system, a first hardware thread and a second hardware thread in a processor core; and viewing, by a user application, the first hardware thread and the second hardware thread as a single CPU object.

Abstract: In an embodiment of the invention, a method for dynamic hardware multithreading, includes: using a hardware halt function or a hardware yield function in a processor core in order to enable or disable a hardware thread that shares the core; wherein the hardware thread is disabled by placing the hardware thread in a halt state or yield state, and allowing another hardware thread to utilize the core.

Abstract: A determination of processor core utilization by a plurality of hardware threads over a time interval is made through a division of a length of the time interval by a total count of the plurality of hardware threads.