Abstract: In one embodiment, a method includes reading a codeword stored to a memory, computing a syndrome word based on a product of the codeword and a parity check matrix derived from a linear block code, setting a flag to a first value indicating that the codeword includes no errors in response to a first determination requiring that the syndrome word is an all-zero vector, setting the flag to a second value indicating that the codeword includes exactly one single-bit error in response to a second determination requiring that the syndrome word equals a column of the parity check matrix, setting the flag to a third value indicating that the codeword includes an odd number of multiple bit errors in response to a third determination, and setting the flag to a fourth value indicating that the codeword includes an even number of multiple bit errors in response to a fourth determination.

Abstract: Provided is a data storage drive for encrypting data, comprising a microprocessor and circuitry coupled to the microprocessor and adapted to receive a session encrypted data key and to decrypt the session encrypted data key using a session key, wherein a result is a data key that is capable of being used to encrypt clear text and to decrypt cipher text written to a storage medium. Also provided is a system, comprising a microprocessor and circuitry coupled to the microprocessor and adapted to receive a session encrypted data key and to decrypt the session encrypted data key using a private key, wherein a result is a secret key that is capable of being used to encrypt clear text and to decrypt cipher text written to a storage medium.

Abstract: In one embodiment, a method includes reading a codeword stored to a memory, computing a syndrome word based on a product of the codeword and a parity check matrix derived from a linear block code, setting a flag to a first value indicating that the codeword includes no errors in response to a first determination requiring that the syndrome word is an all-zero vector, setting the flag to a second value indicating that the codeword includes exactly one single-bit error in response to a second determination requiring that the syndrome word equals a column of the parity check matrix, setting the flag to a third value indicating that the codeword includes an odd number of multiple bit errors in response to a third determination, and setting the flag to a fourth value indicating that the codeword includes an even number of multiple bit errors in response to a fourth determination.

Abstract: Provided is a data storage drive for encrypting data, comprising a microprocessor and circuitry coupled to the microprocessor and adapted to receive a session encrypted data key and to decrypt the session encrypted data key using a session key, wherein a result is a data key that is capable of being used to encrypt clear text and to decrypt cipher text written to a storage medium. Also provided is a system, comprising a microprocessor and circuitry coupled to the microprocessor and adapted to receive a session encrypted data key and to decrypt the session encrypted data key using a private key, wherein a result is a secret key that is capable of being used to encrypt clear text and to decrypt cipher text written to a storage medium.

Abstract: Provided is a data storage drive for encrypting data, comprising a microprocessor and circuitry coupled to the microprocessor and adapted to receive a session encrypted data key and to decrypt the session encrypted data key using a session key, wherein a result is a data key that is capable of being used to encrypt clear text and to decrypt cipher text written to a storage medium. Also provided is a system, comprising a microprocessor and circuitry coupled to the microprocessor and adapted to receive a session encrypted data key and to decrypt the session encrypted data key using a private key, wherein a result is a secret key that is capable of being used to encrypt clear text and to decrypt cipher text written to a storage medium.

Abstract: In one embodiment, a method includes loading first data into a first buffer of an interposer during a first time period and loading second data into a second buffer of the interposer and performing a first decoding operation on the first data using a first decoder during a second time period. The method includes loading third data into a third buffer of the interposer, performing the first decoding operation on the second data using the first decoder, and performing a second decoding operation on the first data using a second decoder during a third time period. Moreover, the method includes loading fourth data into a fourth buffer of the interposer, performing the first decoding operation on the third data using the first decoder, and performing the second decoding operation on the second data during a fourth time period. The first and second decoding operations are C1 or C2 decoding operations.

Abstract: Provided is a data storage drive for encrypting data, comprising a microprocessor and circuitry coupled to the microprocessor and adapted to receive a session encrypted data key and to decrypt the session encrypted data key using a session key, wherein a result is a data key that is capable of being used to encrypt clear text and to decrypt cipher text written to a storage medium. Also provided is a system, comprising a microprocessor and circuitry coupled to the microprocessor and adapted to receive a session encrypted data key and to decrypt the session encrypted data key using a private key, wherein a result is a secret key that is capable of being used to encrypt clear text and to decrypt cipher text written to a storage medium.

Abstract: A method and system for generating ciphertext and message authentication codes utilizing shared hardware are disclosed. According to one embodiment, a method is provided of generating ciphertext message data and message authentication codes utilizing shared authenticated encryption unit hardware. In the described embodiment, plaintext message data is received at an authenticated encryption unit which comprises first and second authenticated encryption hardware modules. Thereafter, a first message authentication code (MAC) associated with a first authenticated encryption mode and a second MAC associated with a second authenticated encryption mode are generated. More specifically, the first MAC is generated utilizing the plaintext message data and first authenticated encryption hardware module and ciphertext message data and the second MAC are generated utilizing the plaintext message data and second authenticated encryption hardware module.

Abstract: A method for equalizing the bandwidth of requesters using a shared memory system is disclosed. In one embodiment, such a method includes receiving multiple access requests to access a shared memory system. Each access request originates from a different requester coupled to the shared memory system. The method then determines which of the access requests has been waiting the longest to access the shared memory system. The access requests are then ordered so that the access request that has been waiting the longest is transmitted to the shared memory system after the other access requests. The requester associated with the longest-waiting access request may then transmit additional access requests to the shared memory system immediately after the longest-waiting access request has been transmitted. A corresponding apparatus and computer program product are also disclosed.

Abstract: A method and system for generating ciphertext and message authentication codes utilizing shared hardware are disclosed. According to one embodiment, a method is provided of generating ciphertext message data and message authentication codes utilizing shared authenticated encryption unit hardware. In the described embodiment, plaintext message data is received at an authenticated encryption unit which comprises first and second authenticated encryption hardware modules. Thereafter, a first message authentication code (MAC) associated with a first authenticated encryption mode and a second MAC associated with a second authenticated encryption mode are generated. More specifically, the first MAC is generated utilizing the plaintext message data and first authenticated encryption hardware module and ciphertext message data and the second MAC are generated utilizing the plaintext message data and second authenticated encryption hardware module.

Abstract: A method and system for generating ciphertext and message authentication codes utilizing shared hardware are disclosed. According to one embodiment, a method is provided of generating ciphertext message data and message authentication codes utilizing shared authenticated encryption unit hardware. In the described embodiment, plaintext message data is received at an authenticated encryption unit which comprises first and second authenticated encryption hardware modules. Thereafter, a first message authentication code (MAC) associated with a first authenticated encryption mode and a second MAC associated with a second authenticated encryption mode are generated. More specifically, the first MAC is generated utilizing the plaintext message data and first authenticated encryption hardware module and ciphertext message data and the second MAC are generated utilizing the plaintext message data and second authenticated encryption hardware module.

Abstract: A method, system, and apparatus for dynamically validating a data encryption operation are disclosed. In one embodiment, a method is provided which comprises decrypting a first sequential data element of a plurality of data elements substantially in parallel with the encryption of a second sequential data element of the plurality, where the first element comprises first data and first encryption validation metadata. In response to the decryption, second encryption validation metadata is generated utilizing the first data. Thereafter, a determination is made whether the first element has been validly encrypted based upon a comparison of the first and second metadata. In other embodiments, an encryption validation indicator may be generated (e.g., to notify a user of a detected encryption error and/or to mark a portion of data for re-encryption), further encryption operations may be suspended, and/or the storage of the first data element may be controlled following such a determination.

Abstract: A method and system for generating ciphertext and message authentication codes utilizing shared hardware are disclosed. According to one embodiment, a method is provided of generating ciphertext message data and message authentication codes utilizing shared authenticated encryption unit hardware. In the described embodiment, plaintext message data is received at an authenticated encryption unit which comprises first and second authenticated encryption hardware modules. Thereafter, a first message authentication code (MAC) associated with a first authenticated encryption mode and a second MAC associated with a second authenticated encryption mode are generated. More specifically, the first MAC is generated utilizing the plaintext message data and first authenticated encryption hardware module and ciphertext message data and the second MAC are generated utilizing the plaintext message data and second authenticated encryption hardware module.

Abstract: A method and system for generating ciphertext and message authentication codes utilizing shared hardware are disclosed. According to one embodiment, a method is provided of generating ciphertext message data and message authentication codes utilizing shared authenticated encryption unit hardware. In the described embodiment, plaintext message data is received at an authenticated encryption unit which comprises first and second authenticated encryption hardware modules. Thereafter, a first message authentication code (MAC) associated with a first authenticated encryption mode and a second MAC associated with a second authenticated encryption mode are generated. More specifically, the first MAC is generated utilizing the plaintext message data and first authenticated encryption hardware module and ciphertext message data and the second MAC are generated utilizing the plaintext message data and second authenticated encryption hardware module.

Abstract: A data storage system has error detecting and correcting system having three error codes. The data are arranged logically as a three-dimensional array consisting of a plurality of logically rectangular blocks of data. Each block of data has columns and rows of data. A first error code that corrects errors creates a first redundancy in each of the columns. A like-positioned block row of data in each of the blocks constitutes an array row of data. The array rows are grouped into sets of array rows, the number of array rows in each set vary inversely with a number of tracks of a record medium that concurrently receive the data for recording. Each set of data are recorded serially by bit in respective tracks of the tape record medium. Before recording, the block rows are logically rotated (end-around shifted) within each of the array rows.