Abstract: System and method are provided where parcels or packages are associated or grouped, into logical group or logical containerization of parcels or packages, without need for physical container, such that parcels or packages can be tracked as a group, for example with a unique group ID. Logical group may be tracked within specified logical zone on conveyor, transported, sorted and/or otherwise processed as unique logical group without need to be contained in physical container. System and method for automated sortation can accumulate set number or set volume of packages, and then process the accumulated set number or volume of packages.

Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon FET. A ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. A gate can then be grown on the ferroelectric layer.

Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers, such as undoped semiconductor layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be preferentially etched away, leaving the doped semiconductor layers as fins for a ribbon FET. In another embodiment, an interlayer can be deposited on top of a semiconductor layer, and a ferroelectric layer can be deposited on the interlayer. The interlayer can bridge a gap in lattice parameters between the semiconductor layer and the ferroelectric layer.

Abstract: Technologies for a transistor with a thin-film ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a thin layer of scandium aluminum nitride (ScxAl1-xN) ferroelectric gate dielectric. The channel of the transistor may be, e.g., gallium nitride or molybdenum disulfide. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one-transistor memory cell.

Abstract: In one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the FE material. The FE material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.

Abstract: In one embodiment, a transistor device includes a gate material layer on a substrate, a ferroelectric (FE) material layer on the gate material, a semiconductor channel material layer on the FE material layer, a first source/drain material on the FE material layer and adjacent the semiconductor channel material layer, and a second source/drain material on the FE material layer and adjacent the semiconductor channel material layer and on an opposite side of the semiconductor channel material layer from the first source/drain material. A first portion of the FE material layer is directly between the gate material and the first source/drain material, and a second portion of the FE material layer is directly between the gate material and the second source/drain material.

Abstract: According to an aspect, a clevis assembly includes a shackle having two ends, each end respectively including an aperture, a structure connecting the apertures and housing a bearing, and a shearing device that includes a frangible point and is in operable communication with the bearing, where the shearing device is housed in a hollow portion of the structure.

Abstract: According to an aspect, a clevis assembly includes a shackle having two ends, each end respectively including an aperture, a structure connecting the apertures and housing a bearing, and a shearing device that includes a frangible point and is in operable communication with the bearing, where the shearing device is housed in a hollow portion of the structure.

Abstract: A flight control pump system includes an electrical machine configured to operate in a motor mode and in a generator mode. A pump is operatively connected to be driven by the electrical machine in the motor mode. An overriding clutch is operatively connected to the electrical machine and to the pump to transfer torque from a main transmission to drive the pump and the electrical machine in the generator mode, and to decouple the main transmission from the electrical machine and the pump in the motor mode.