Patents by Inventor Scott Jansen

Scott Jansen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200161720
    Abstract: An electrode (110) for an electrochemical cell, comprising a conductive, porous, hydrophilic, gas-permeable and a liquid-permeable liquid-side layer (111) having a liquid-facing side (116), and a non-conductive, porous, hydrophobic, gas-permeable and liquid-impermeable gas-side layer (112) having a gas-facing side (117). Gas-producing electrochemical reactions are promoted at an interface (115) between the liquid-side layer (111) and the gas-side layer (112) by a beneficial relationship of capillary pressures of the electrode layers. The liquid-side layer (111) exhibits a repulsive capillary pressure in the liquid electrolyte (113) of the cell (110) and the gas-side layer exhibits an attractive capillary pressure in the liquid electrolyte (113).
    Type: Application
    Filed: May 25, 2018
    Publication date: May 21, 2020
    Applicant: AQUAHYDREX PTY LTD
    Inventors: Gerhard Frederick SWIEGERS, Scott JANSEN, Nathan SCHUH, Jared James Cullen SMITH, Adrian Allan GESTOS, James Scott GREER, Mark Simbajon ROMANO, Prerna TIWARI
  • Publication number: 20180363154
    Abstract: Disclosed are electrochemical cells and methods of operation. In one aspect is disclosed an electrochemical cell that has a liquid-electrolyte or a gel-electrolyte, the cell comprising: an electrode, preferably a gas diffusion electrode; a busbar attached to a current collector of the electrode; and a second electrode to which the first electrode is connected in electrical series. In another aspect is disclosed a plurality of electrochemical cells, comprising: a first electrochemical cell comprising a first cathode and a first anode, wherein at least one of the first cathode and the first anode is a gas diffusion electrode; a second electrochemical cell comprising a second cathode and a second anode, wherein at least one of the second cathode and the second anode is a gas diffusion electrode; wherein, the first cathode is electrically connected in series to the second anode by an electron conduction pathway.
    Type: Application
    Filed: December 14, 2016
    Publication date: December 20, 2018
    Inventors: Gerhard Frederick SWIEGERS, Eric Austin SEYMOUR, Jordan Christopher HAAS, Scott JANSEN, Byron John BURKILL
  • Publication number: 20170198999
    Abstract: A rifle action for a firearm includes a receiver, a breech bolt and a mechanical case ejector. The receiver has a receiver bore, a first sidewall with an opening for ejecting shell casings, and a second sidewall with a blind pocket on a side facing the receiver bore. The ejector is rotatably mounted by a pin that extends vertically between top and bottom surfaces of the blind pocket. The ejector has a base that fits into the blind pocket and a finger that extends into the receiver bore. The ejector has a first position in which the finger is located out of a path of movement of the breech bolt, and a second position in which the finger extends into a path of movement of the breech bolt upon rearward movement of the bolt to eject shell casings from the receiver bore. The blind pocket can be formed by EDM.
    Type: Application
    Filed: January 11, 2016
    Publication date: July 13, 2017
    Inventors: Anthony Goddard, Aaron Tritsch, Scott Jansen, Jevon Homitzky, Eric Stieb
  • Patent number: 9373717
    Abstract: Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: June 21, 2016
    Assignee: Infineon Technologies AG
    Inventors: Alois Gutmann, Roland Hampp, Scott Jansen
  • Publication number: 20150263197
    Abstract: A photovoltaic device includes a substrate and has a transparent conductive oxide layer, a conductive back layer, and at least one intermediate semiconductor layer formed thereon. An isolation scribe divides and electrically isolates the oxide layer, the back layer and the semiconductor layer to define two photovoltaic cells. A conductor extends across the isolation scribe and connects the back layer of one photovoltaic cell to the oxide layer of the other photovoltaic cell.
    Type: Application
    Filed: March 13, 2015
    Publication date: September 17, 2015
    Inventors: Scott Jansen, Casimir P. Kotarba, Jonathan Pappas, Rick Powell, Yann Roussillon, Erica Van Nortwick, Charles Wickersham
  • Publication number: 20150137253
    Abstract: Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.
    Type: Application
    Filed: December 9, 2014
    Publication date: May 21, 2015
    Inventors: Alois Gutmann, Roland Hampp, Scott Jansen
  • Patent number: 8907444
    Abstract: Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: December 9, 2014
    Assignee: Infineon Technologies AG
    Inventors: Alois Gutmann, Roland Hampp, Scott Jansen
  • Patent number: 8361879
    Abstract: Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: January 29, 2013
    Assignee: Infineon Technologies AG
    Inventors: Alois Gutmann, Roland Hampp, Scott Jansen
  • Patent number: 7679083
    Abstract: Semiconductor integrated test structures are designed for electron beam inspection of semiconductor wafers. The test structures include pattern features that are formed in designated test regions of the wafer concurrently with pattern features of integrated circuits formed on the wafer. The test structures include conductive structures that are designed to enable differential charging between defective and non-defective features (or defective and non-defection portions of a given feature) to facilitate voltage contrast defect detection of CMOS devices, for example, using a single, low energy electron beam scan, notwithstanding the existence of p/n junctions in the wafer substrate or other elements/features.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: March 16, 2010
    Assignees: Samsung Electronics Co., Ltd., International Business Machines Corporation, Infineon Technologies AG
    Inventors: Min Chul Sun, Scott Jansen, Randy Mann, Oliver D. Patterson
  • Publication number: 20090283852
    Abstract: Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.
    Type: Application
    Filed: May 19, 2008
    Publication date: November 19, 2009
    Inventors: Alois Gutmann, Roland Hampp, Scott Jansen
  • Publication number: 20080237586
    Abstract: Semiconductor integrated test structures are designed for electron beam inspection of semiconductor wafers. The test structures include pattern features that are formed in designated test regions of the wafer concurrently with pattern features of integrated circuits formed on the wafer. The test structures include conductive structures that are designed to enable differential charging between defective and non-defective features (or defective and non-defection portions of a given feature) to facilitate voltage contrast defect detection of CMOS devices, for example, using a single, low energy electron beam scan, notwithstanding the existence of p/n junctions in the wafer substrate or other elements/features.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Min Chul Sun, Scott Jansen, Randy Mann, Oliver D. Patterson
  • Patent number: 4563564
    Abstract: A resistor formed by a film of resistive material deposited on a dielectric substrate is trimmed by removing resistive material along a line such that the film is divided into at least two discrete areas, one, and only one, of which areas includes two terminal portions of the film.
    Type: Grant
    Filed: January 30, 1984
    Date of Patent: January 7, 1986
    Assignee: Tektronix, Inc.
    Inventors: Bret Ericsen, John C. Hastings, Desmond L. Murphy, Scott Jansen