Patents by Inventor Scott Janus
Scott Janus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240078630Abstract: Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.Type: ApplicationFiled: October 19, 2023Publication date: March 7, 2024Applicant: Intel CorporationInventors: Subramaniam Maiyuran, Durgaprasad Bilagi, Joydeep Ray, Scott Janus, Sanjeev Jahagirdar, Brent Insko, Lidong Xu, Abhishek R. Appu, James Holland, Vasanth Ranganathan, Nikos Kaburlasos, Altug Koker, Xinmin Tian, Guei-Yuan Lueh, Changliang Wang
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Patent number: 11892950Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.Type: GrantFiled: July 15, 2022Date of Patent: February 6, 2024Assignee: INTEL CORPORATIONInventors: Vikranth Vemulapalli, Lakshminarayanan Striramassarma, Mike MacPherson, Aravindh Anantaraman, Ben Ashbaugh, Murali Ramadoss, William B. Sadler, Jonathan Pearce, Scott Janus, Brent Insko, Vasanth Ranganathan, Kamal Sinha, Arthur Hunter, Jr., Prasoonkumar Surti, Nicolas Galoppo von Borries, Joydeep Ray, Abhishek R. Appu, ElMoustapha Ould-Ahmed-Vall, Altug Koker, Sungye Kim, Subramaniam Maiyuran, Valentin Andrei
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Patent number: 11880928Abstract: Apparatus and method for a hierarchical beam tracer.Type: GrantFiled: April 19, 2022Date of Patent: January 23, 2024Assignee: INTEL CORPORATIONInventors: Scott Janus, Prasoonkumar Surti, Karthik Vaidyanathan, Alexey Supikov, Gabor Liktor, Carsten Benthin, Philip Laws, Michael Doyle
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Patent number: 11861761Abstract: Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.Type: GrantFiled: November 11, 2020Date of Patent: January 2, 2024Assignee: Intel CorporationInventors: Subramaniam Maiyuran, Durgaprasad Bilagi, Joydeep Ray, Scott Janus, Sanjeev Jahagirdar, Brent Insko, Lidong Xu, Abhishek R. Appu, James Holland, Vasanth Ranganathan, Nikos Kaburlasos, Altug Koker, Xinmin Tian, Guei-Yuan Lueh, Changliang Wang
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Publication number: 20230386417Abstract: Often when there is a glare on a display screen the user may be able to mitigate the glare by tilting or otherwise moving the screen or changing their viewing position. However, when driving a car there are limited options for overcoming glares on the dashboard, especially when you are driving for a long distance in the same direction. Embodiments are directed to eliminating such glare. Other embodiments are related to mixed reality (MR) and filling in occluded areas.Type: ApplicationFiled: May 24, 2023Publication date: November 30, 2023Applicant: Intel CorporationInventors: Arthur J. Runyan, Richmond Hicks, Nausheen Ansari, Narayan Biswal, Ya-Ti Peng, Abhishek R. Appu, Wen-Fu Kao, Sang-Hee Lee, Joydeep Ray, Changliang Wang, Satyanarayana Avadhanam, Scott Janus, Gary Smith, Nilesh V. Shah, Keith W. Rowe, Robert J. Johnston
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Publication number: 20230360272Abstract: Example methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement multi-plane image (MPI) compression are disclosed. Example apparatus disclosed herein include an interface to access an input multiplane image stack corresponding to a source camera viewpoint, the input multiplane image stack including a plurality of texture images and a corresponding plurality of alpha images, ones of the alpha images including pixel values representative of transparency of corresponding pixels in respective ones of the texture images. Disclosed example apparatus also include a compressed image encoder to at least one of (i) convert the plurality of texture images to a single composite texture image to generate a compressed multiplane image stack, or (ii) convert the plurality of alpha images to a single composite alpha image to generate the compressed multiplane image stack. In some disclosed examples, the interface is to output the compressed multiplane image stack.Type: ApplicationFiled: June 18, 2021Publication date: November 9, 2023Inventors: Scott JANUS, Jill BOYCE, Atul DIVEKAR, Jason TANNER, Sumit BHATIA, Penne Y. LEE
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Publication number: 20230360307Abstract: One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural network hardware block configured to perform operations associated with a neural network configured to determine a prefetch pattern for the cache memory prefetcher.Type: ApplicationFiled: May 1, 2023Publication date: November 9, 2023Applicant: Intel CorporationInventors: HUGUES LABBE, DARREL PALKE, SHERINE ABDELHAK, JILL BOYCE, VARGHESE GEORGE, SCOTT JANUS, ADAM LAKE, ZHIJUN LEI, ZHENGMIN LI, MIKE MACPHERSON, CARL MARSHALL, SELVAKUMAR PANNEER, PRASOONKUMAR SURTI, KARTHIK VEERAMANI, DEEPAK VEMBAR, VALLABHAJOSYULA SRINIVASA SOMAYAZULU
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Publication number: 20230351543Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to detect zero value elements within a vector or a set of packed data elements output by a processing resource and generate metadata to indicate a location of the zero value elements within the plurality of data elements.Type: ApplicationFiled: May 2, 2023Publication date: November 2, 2023Applicant: Intel CorporationInventors: Joydeep Ray, Scott Janus, Varghese George, Subramaniam Maiyuran, Altug Koker, Abhishek Appu, Prasoonkumar Surti, Vasanth Ranganathan, Valentin Andrei, Ashutosh Garg, Yoav Harel, Arthur Hunter, JR., SungYe Kim, Mike Macpherson, Elmoustapha Ould-Ahmed-Vall, William Sadler, Lakshminarayanan Striramassarma, Vikranth Vemulapalli
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Publication number: 20230260075Abstract: Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a state of multiple intellectual property (IP) cores that have access to a common cache via a central fabric is observed. Responsive to the observed state being indicative of performance of a standalone workload by a first IP core of the multiple IP cores, the common cache is treated as a local cache of the first IP core by powering off the central fabric and causing the first IP core to access the common cache via a low power access path between the first IP core and the common cache that is outside of the central fabric.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Applicant: Intel CorporationInventors: Subramaniam Maiyuran, Durgaprasad Bilagi, Joydeep Ray, Scott Janus, Sanjeev Jahagirdar, Brent Insko, Lidong Xu, Abhishek R. Appu, James Holland, Vasanth Ranganathan, Nikos Kaburlasos, Altug Koker, Xinmin Tian, Guei-Yuan Lueh, Changliang Wang
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Patent number: 11699404Abstract: Often when there is a glare on a display screen the user may be able to mitigate the glare by tilting or otherwise moving the screen or changing their viewing position. However, when driving a car there are limited options for overcoming glares on the dashboard, especially when you are driving for a long distance in the same direction. Embodiments are directed to eliminating such glare. Other embodiments are related to mixed reality (MR) and filling in occluded areas.Type: GrantFiled: March 24, 2022Date of Patent: July 11, 2023Assignee: Intel CorporationInventors: Arthur J. Runyan, Richmond Hicks, Nausheen Ansari, Narayan Biswal, Ya-Ti Peng, Abhishek R. Appu, Wen-Fu Kao, Sang-Hee Lee, Joydeep Ray, Changliang Wang, Satyanarayana Avadhanam, Scott Janus, Gary Smith, Nilesh V. Shah, Keith W. Rowe, Robert J. Johnston
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Patent number: 11676322Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.Type: GrantFiled: October 13, 2021Date of Patent: June 13, 2023Assignee: Intel CorporationInventors: Hugues Labbe, Darrel Palke, Sherine Abdelhak, Jill Boyce, Varghese George, Scott Janus, Adam Lake, Zhijun Lei, Zhengmin Li, Mike Macpherson, Carl Marshall, Selvakumar Panneer, Prasoonkumar Surti, Karthik Veeramani, Deepak Vembar, Vallabhajosyula Srinivasa Somayazulu
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Patent number: 11676239Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.Type: GrantFiled: June 3, 2021Date of Patent: June 13, 2023Assignee: Intel CorporationInventors: Joydeep Ray, Scott Janus, Varghese George, Subramaniam Maiyuran, Altug Koker, Abhishek Appu, Prasoonkumar Surti, Vasanth Ranganathan, Andrei Valentin, Ashutosh Garg, Yoav Harel, Arthur Hunter, Jr., SungYe Kim, Mike Macpherson, Elmoustapha Ould-Ahmed-Vall, William Sadler, Lakshminarayanan Striramassarma, Vikranth Vemulapalli
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Patent number: 11627307Abstract: Embodiments are generally directed to transport controlled video coding. An embodiment of an apparatus includes one or more processors to process data; a memory to store data, including data for video streaming; and a video processing mechanism including an encoder and a transport mechanism, wherein the video processing mechanism is to generate a prediction of channel throughput for a network channel, encode one or more bitstreams based on the prediction, including encoding a plurality of bitstreams including a first bitstream and a second bitstream if the prediction indicates an increase or decrease in channel throughput and encoding a single bitstream if the prediction indicates a stable channel throughput; and select a bitstream of the one or more bitstreams for a current frame.Type: GrantFiled: September 28, 2018Date of Patent: April 11, 2023Assignee: INTEL CORPORATIONInventors: Changliang Wang, Ximin Zhang, Jill Boyce, Sang-Hee Lee, Scott Janus, Yunbiao Lin
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Patent number: 11620256Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.Type: GrantFiled: April 28, 2022Date of Patent: April 4, 2023Assignee: Intel CorporationInventors: Altug Koker, Joydeep Ray, Ben Ashbaugh, Jonathan Pearce, Abhishek Appu, Vasanth Ranganathan, Lakshminarayanan Striramassarma, Elmoustapha Ould-Ahmed-Vall, Aravindh Anantaraman, Valentin Andrei, Nicolas Galoppo Von Borries, Varghese George, Yoav Harel, Arthur Hunter, Jr., Brent Insko, Scott Janus, Pattabhiraman K, Mike Macpherson, Subramaniam Maiyuran, Marian Alin Petre, Murali Ramadoss, Shailesh Shah, Kamal Sinha, Prasoonkumar Surti, Vikranth Vemulapalli
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Publication number: 20230063678Abstract: Methods, systems and apparatuses may provide for technology that detects virtual background content and real-time foreground content associated with a video session, wherein the real-time foreground content depicts a plurality of participants from different physical environments. The technology may also apply a visual correction to one or more of the real-time foreground content or the virtual background content, wherein the visual correction reduces a difference between the real-time foreground content and the virtual background content with respect to one or more lighting parameters and two or more of the plurality of participants. Additionally, the technology may generate a composite result based on the real-time foreground content, the virtual background content, and the visual correction.Type: ApplicationFiled: September 2, 2021Publication date: March 2, 2023Inventors: Scott Janus, Deepak Vembar
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Publication number: 20230051190Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.Type: ApplicationFiled: July 15, 2022Publication date: February 16, 2023Applicant: Intel CorporationInventors: Vikranth Vemulapalli, Lakshminarayanan Striramassarma, Mike MacPherson, Aravindh Anantaraman, Ben Ashbaugh, Murali Ramadoss, William B. Sadler, Jonathan Pearce, Scott Janus, Brent Insko, Vasanth Ranganathan, Kamal Sinha, Arthur Hunter, JR., Prasoonkumar Surti, Nicolas Galoppo von Borries, Joydeep Ray, Abhishek R. Appu, ElMoustapha Ould-Ahmed-Vall, Altug Koker, Sungye Kim, Subramaniam Maiyuran, Valentin Andrei
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Patent number: 11557085Abstract: Embodiments are directed to neural network processing for multi-object three-dimensional (3D) modeling. An embodiment of a computer-readable storage medium includes executable computer program instructions for obtaining data from multiple cameras, the data including multiple images, and generating a 3D model for 3D imaging based at least in part on the data from the cameras, wherein generating the 3D model includes one or more of performing processing with a first neural network to determine temporal direction based at least in part on motion of one or more objects identified in an image of the multiple images or performing processing with a second neural network to determine semantic content information for an image of the multiple images.Type: GrantFiled: December 4, 2020Date of Patent: January 17, 2023Assignee: Intel CorporationInventors: Jill Boyce, Soethiha Soe, Selvakumar Panneer, Adam Lake, Nilesh Jain, Deepak Vembar, Glen J. Anderson, Varghese George, Carl Marshall, Scott Janus, Saurabh Tangri, Karthik Veeramani, Prasoonkumar Surti
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Publication number: 20220350751Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received. In one embodiment, the cache memory configured to be partitioned into multiple cache regions, wherein the multiple cache regions include a first cache region having a cache eviction policy with a configurable level of data persistence.Type: ApplicationFiled: July 12, 2022Publication date: November 3, 2022Applicant: Intel CorporationInventors: Altug Koker, Joydeep Ray, Elmoustapha Ould-Ahmed-Vall, Abhishek Appu, Aravindh Anantaraman, Valentin Andrei, Durgaprasad Bilagi, Varghese George, Brent Insko, Sanjeev Jahagirdar, Scott Janus, Pattabhiraman K, SungYe Kim, Subramaniam Maiyuran, Vasanth Ranganathan, Lakshminarayanan Striramassarma, Xinmin Tian
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Publication number: 20220327763Abstract: Apparatus and method for a hierarchical beam tracer.Type: ApplicationFiled: April 19, 2022Publication date: October 13, 2022Inventors: Scott JANUS, Prasoonkumar SURTI, Karthik VAIDYANATHAN, Alexey SUPIKOV, Gabor LIKTOR, Carsten BENTHIN, Philip LAWS, Michael DOYLE
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Publication number: 20220284867Abstract: Often when there is a glare on a display screen the user may be able to mitigate the glare by tilting or otherwise moving the screen or changing their viewing position. However, when driving a car there are limited options for overcoming glares on the dashboard, especially when you are driving for a long distance in the same direction. Embodiments are directed to eliminating such glare. Other embodiments are related to mixed reality (MR) and filling in occluded areas.Type: ApplicationFiled: March 24, 2022Publication date: September 8, 2022Inventors: Arthur J. Runyan, Richmond Hicks, Nausheen Ansari, Narayan Biswal, Ya-Ti Peng, Abhishek R. Appu, Wen-Fu Kao, Sang-Hee Lee, Joydeep Ray, Changliang Wang, Satyanarayana Avadhanam, Scott Janus, Gary Smith, Nilesh V. Shah, Keith W. Rowe, Robert J. Johnston