Patents by Inventor Scott Kimura
Scott Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8731071Abstract: A system for performing finite input response filtering. The system includes an array of random access memories (RAMs) for storing at least one two-dimensional (2D) block of pixel data. The pixel data is stored such that one of each type of column or row from the 2D block of pixel data is stored per RAM. A control block provides address translation between the 2D block of pixel data and corresponding addresses in the array of RAMs. An input crossbar writes pixel data to the array of RAMs as directed by the control block. An output crossbar simultaneously reads pixel data from each of the array of RAMs and passes the data to an appropriate replicated data path, as directed by the control block. A single instruction multiple data path block includes a plurality of replicated data paths for simultaneously performing the FIR filtering, as directed by the control block.Type: GrantFiled: December 15, 2005Date of Patent: May 20, 2014Assignee: Nvidia CorporationInventor: Scott A. Kimura
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Patent number: 8060549Abstract: A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained. The accumulating utilizes a shared adder, and includes means for directing initial inputs and intermediate result values.Type: GrantFiled: August 31, 2006Date of Patent: November 15, 2011Assignee: Pasternak Solutions, LLCInventors: Stephen Clark Purcell, Scott Kimura, Mark Wood-Patrick
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Patent number: 8010618Abstract: A method and computer program product includes, at a sender, identifying a forward item including a transmit portion and a retain portion, generating a tag, associating the tag with the retain portion, sending the transmit portion, but not the tag, to a target; at the target, receiving the transmit portion, identifying a return portion corresponding to the transmit portion, independently generating the tag, associating the tag with the return portion, sending the return portion and the tag to the sender; and at the sender, receiving the return portion and the tag, identifying the retain portion using the tag, and associating the return portion with the retain portion to create a reverse item.Type: GrantFiled: August 31, 2006Date of Patent: August 30, 2011Inventors: Stephen Clark Purcell, Scott Kimura
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Patent number: 7822012Abstract: A method and apparatus includes identifying an address portion of a first message in an address slice of a switch, the first message associated with a first priority, the address portion of the first message including a first routing portion specifying a network resource; identifying an address portion of a second message in the address slice, the second message associated with a second priority, the address portion of the second message including a second routing portion specifying the same network resource; identifying a non-address portion of the first message in a non-address slice of the switch; identifying a non-address portion of the second message in the non-address slice, wherein neither of the non-address portions includes a routing portion specifying the network resource; selecting, independently in each slice, the same one of the first and second messages based on the first and second priorities; transferring the address portion of the selected message to the network resource specified by the routType: GrantFiled: May 23, 2005Date of Patent: October 26, 2010Inventors: Stephen Clark Purcell, Scott Kimura
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Patent number: 7584320Abstract: A memory crossbar adapted to transmit a memory transaction to a network resource. The memory crossbar includes a plurality of input ports. Each of the plurality of input ports includes a TAGS generator and a queue adapted to receive a first portion of a first memory transaction and a first portion of a second memory transaction. Each of the plurality of inputs ports also includes an arbiter coupled to the queue and adapted to independently select either the first portion of the first memory transaction or the first portion of the second memory transaction based on a priority associated with the first portion of the first memory transaction and the first portion of the second memory transaction and a multiplexer coupled to the arbiter.Type: GrantFiled: September 25, 2007Date of Patent: September 1, 2009Assignee: Pasternak Solutions LLCInventors: Stephen Clark Purcell, Scott Kimura
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Patent number: 7509361Abstract: A method and apparatus for generating random number outputs utilized in generating a noise function at a given location in space. The method consists of partitioning selected portions of the random number generation process to achieve outputs in parallel. The relevant parallel outputs are weighted by effect and then summed together to give the amplitude of the noise function at the given location.Type: GrantFiled: May 30, 2006Date of Patent: March 24, 2009Assignee: Pastemak Solutions LLCInventors: Stephen Clark Purcell, Scott Kimura, Rajeshwaran Selvanesan
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Patent number: 7426603Abstract: A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory transaction addressed to one of the memory banks, the memory bus incapable of transmitting the plurality of memory transactions simultaneously; identifying a plurality of bank readiness signals, each bank readiness signal indicating the readiness of one of the memory banks to accept a memory transaction; and selecting one of the memory transactions for transmission over the memory bus based on the bank readiness signals.Type: GrantFiled: August 4, 2006Date of Patent: September 16, 2008Assignee: Pasternak Solutions, LLCInventors: Stephen Clark Purcell, Scott Kimura
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Publication number: 20080126466Abstract: A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained. The accumulating utilizes a shared adder, and includes means for directing initial inputs and intermediate result values.Type: ApplicationFiled: August 31, 2006Publication date: May 29, 2008Inventors: Stephen Clark Purcell, Scott Kimura, Mark L. Wood Patrick
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Publication number: 20080098151Abstract: A memory crossbar adapted to transmit a memory transaction to a network resource. The memory crossbar includes a plurality of input ports. Each of the plurality of input ports includes a TAGS generator and a queue adapted to receive a first portion of a first memory transaction and a first portion of a second memory transaction. Each of the plurality of inputs ports also includes an arbiter coupled to the queue and adapted to independently select either the first portion of the first memory transaction or the first portion of the second memory transaction based on a priority associated with the first portion of the first memory transaction and the first portion of the second memory transaction and a multiplexer coupled to the arbiter.Type: ApplicationFiled: September 25, 2007Publication date: April 24, 2008Applicant: PASTERNAK SOLUTIONS LLCInventors: Stephen Purcell, Scott Kimura
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Patent number: 7275126Abstract: A memory crossbar adapted to transmit a memory transaction to a network resource. The memory crossbar includes a plurality of input ports. Each of the plurality of input ports includes a TAGS generator and a queue adapted to receive a first portion of a first memory transaction and a first portion of a second memory transaction. Each of the plurality of inputs ports also includes an arbiter coupled to the queue and adapted to independently select either the first portion of the first memory transaction or the first portion of the second memory transaction based on a priority associated with the first portion of the first memory transaction and the first portion of the second memory transaction and a multiplexer coupled to the arbiter.Type: GrantFiled: August 31, 2006Date of Patent: September 25, 2007Assignee: Pasternak Solutions LLCInventors: Stephen Clark Purcell, Scott Kimura
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Patent number: 7249214Abstract: A method and apparatus includes identifying a first portion of a first message in a first slice of a switch, the first message associated with a first priority, the first portion of the first message including a first routing portion specifying a network resource; identifying a second portion of the first message in a second slice of the switch, the second portion of the first message including the first routing portion; identifying a first portion of a second message in the first slice, the second message associated with a second priority, the first portion of the second message including a second routing portion specifying the network resource; identifying a second portion of the second message in the second slice, the second portion of the second message including the second routing portion; selecting, independently in each slice, the same one of the first and second messages based on the first and second priorities; sending the first portion of the selected message from the first slice to the network resoType: GrantFiled: September 1, 2005Date of Patent: July 24, 2007Inventors: Stephen Clark Purcell, Scott Kimura
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Patent number: 7212959Abstract: A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained. The accumulating utilizes a shared adder, and includes means for directing initial inputs and intermediate result values.Type: GrantFiled: August 8, 2001Date of Patent: May 1, 2007Inventors: Stephen Clark Purcell, Scott Kimura, Mark L. Wood Patrick
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Publication number: 20060285377Abstract: A memory crossbar adapted to transmit a memory transaction to a network resource. The memory crossbar includes a plurality of input ports. Each of the plurality of input ports includes a TAGS generator and a queue adapted to receive a first portion of a first memory transaction and a first portion of a second memory transaction. Each of the plurality of inputs ports also includes an arbiter coupled to the queue and adapted to independently select either the first portion of the first memory transaction or the first portion of the second memory transaction based on a priority associated with the first portion of the first memory transaction and the first portion of the second memory transaction and a multiplexer coupled to the arbiter.Type: ApplicationFiled: August 31, 2006Publication date: December 21, 2006Applicant: Pasternak Solutions LLC.Inventors: Stephen Purcell, Scott Kimura
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Publication number: 20060271724Abstract: A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory transaction addressed to one of the memory banks, the memory bus incapable of transmitting the plurality of memory transactions simultaneously; identifying a plurality of bank readiness signals, each bank readiness signal indicating the readiness of one of the memory banks to accept a memory transaction; and selecting one of the memory transactions for transmission over the memory bus based on the bank readiness signals.Type: ApplicationFiled: August 4, 2006Publication date: November 30, 2006Applicant: Pasternak Solutions LLCInventors: Stephen Purcell, Scott Kimura
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Patent number: 7139836Abstract: A method and computer program product includes, at a sender, identifying a forward item including a transmit portion and a retain portion, generating a tag, associating the tag with the retain portion, sending the transmit portion, but not the tag, to a target; at the target, receiving the transmit portion, identifying a return portion corresponding to the transmit portion, independently generating the tag, associating the tag with the return portion, sending the return portion and the tag to the sender; and at the sender, receiving the return portion and the tag, identifying the retain portion using the tag, and associating the return portion with the retain portion to create a reverse item.Type: GrantFiled: August 8, 2001Date of Patent: November 21, 2006Inventors: Stephen Clark Purcell, Scott Kimura
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Patent number: 7107386Abstract: A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory transaction addressed to one of the memory banks, the memory bus incapable of transmitting the plurality of memory transactions simultaneously; identifying a plurality of bank readiness signals, each bank readiness signal indicating the readiness of one of the memory banks to accept a memory transaction; and selecting one of the memory transactions for transmission over the memory bus based on the bank readiness signals.Type: GrantFiled: January 15, 2004Date of Patent: September 12, 2006Assignee: Pasternak Solutions, LLCInventors: Stephen Clark Purcell, Scott Kimura
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Patent number: 7072927Abstract: A method and apparatus for generating random number outputs utilized in generating a noise function at a given location in space. The method consists of partitioning selected portions of the random number generation process to achieve outputs in parallel. The relevant parallel outputs are weighted by effect and then summed together to give the amplitude of the noise function at the given location.Type: GrantFiled: August 8, 2001Date of Patent: July 4, 2006Inventors: Stephen Clark Purcell, Scott Kimura, Rajeshwaran Selvanesan
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Patent number: 7072924Abstract: A method and apparatus for generating random number outputs utilized in generating a noise function at a given location in space. The method consists of partitioning selected portions of the random number generation process to achieve outputs in parallel. The relevant parallel outputs are weighted by effect and then summed together to give the amplitude of the noise function at the given location.Type: GrantFiled: August 25, 2004Date of Patent: July 4, 2006Inventors: Stephen Clark Purcell, Scott Kimura, Rajeshwaran Selvanesan
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Publication number: 20060010281Abstract: A method and apparatus includes identifying a first portion of a first message in a first slice of a switch, the first message associated with a first priority, the first portion of the first message including a first routing portion specifying a network resource; identifying a second portion of the first message in a second slice of the switch, the second portion of the first message including the first routing portion; identifying a first portion of a second message in the first slice, the second message associated with a second priority, the first portion of the second message including a second routing portion specifying the network resource; identifying a second portion of the second message in the second slice, the second portion of the second message including the second routing portion; selecting, independently in each slice, the same one of the first and second messages based on the first and second priorities; sending the first portion of the selected message from the first slice to the network resoType: ApplicationFiled: September 1, 2005Publication date: January 12, 2006Applicant: Pasternak Solutions LLCInventors: Stephen Purcell, Scott Kimura
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Patent number: 6970454Abstract: A method and apparatus includes identifying an address portion of a first message in an address slice of a switch, the first message associated with a first priority, the address portion of the first message including a first routing portion specifying a network resource; identifying an address portion of a second message in the address slice, the second message associated with a second priority, the address portion of the second message including a second routing portion specifying the same network resource; identifying a non-address portion of the first message in a non-address slice of the switch; identifying a non-address portion of the second message in the non-address slice, wherein neither of the non-address portions includes a routing portion specifying the network resource; selecting, independently in each slice, the same one of the first and second messages based on the first and second priorities; transferring the address portion of the selected message to the network resource specified by the routType: GrantFiled: August 9, 2001Date of Patent: November 29, 2005Assignee: Pasternak Solutions LLCInventors: Stephen Clark Purcell, Scott Kimura