Patents by Inventor Scott L. Hunt

Scott L. Hunt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High density trench field effect transistor
    Patent number: 8278702
    Abstract: A semiconductor structure comprises trenches extending into a semiconductor region. Portions of the semiconductor region extend between adjacent trenches forming mesa regions. A gate electrode is in each trench. Well regions of a first conductivity type extend in the semiconductor region between adjacent trenches. Source regions of a second conductivity type are in the well regions. Heavy body regions of the first conductivity type are in the well regions. The source regions and the heavy body regions are adjacent trench sidewalls, and the heavy body regions extend over the source regions along the trench sidewalls to a top surface of the mesa regions.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: October 2, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James Pan, Scott L. Hunt, Dean E. Probst, Hossein Paravi
  • Method for forming a shielded gate trench FET
    Patent number: 8129241
    Abstract: A method for forming a shielded gate field effect transistor (FET) includes forming a plurality of trenches in a semiconductor region and forming a shield electrode in a bottom portion of each trench. The method also includes forming a dielectric layer comprising a first oxide layer and a nitride layer both laterally extending over the shield electrode. The method also includes forming a gate electrode over the dielectric layer.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: March 6, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Scott L. Hunt
  • Method for Forming a Shielded Gate Trench FET
    Publication number: 20110081773
    Abstract: A method for forming a shielded gate field effect transistor (FET) includes forming a plurality of trenches in a semiconductor region and forming a shield electrode in a bottom portion of each trench. The method also includes forming a dielectric layer comprising a first oxide layer and a nitride layer both laterally extending over the shield electrode. The method also includes forming a gate electrode over the dielectric layer.
    Type: Application
    Filed: December 2, 2010
    Publication date: April 7, 2011
    Inventor: Scott L. Hunt
  • Shielded gate trench FET with an inter-electrode dielectric having a nitride layer therein
    Patent number: 7872305
    Abstract: A shielded gate field effect transistor (FET) comprises a plurality of trenches extending into a semiconductor region. A shield electrode is disposed in a bottom portion of each trench, and a gate electrode is disposed over the shield electrode in each trench. An inter-electrode dielectric (IED) extends between the shield electrode and the gate electrode. The IED comprises a first oxide layer and a nitride layer over the first oxide layer.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: January 18, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Scott L. Hunt
  • High density trench field effect transistor
    Publication number: 20100065904
    Abstract: A semiconductor structure comprises trenches extending into a semiconductor region. Portions of the semiconductor region extend between adjacent trenches forming mesa regions. A gate electrode is in each trench. Well regions of a first conductivity type extend in the semiconductor region between adjacent trenches. Source regions of a second conductivity type are in the well regions. Heavy body regions of the first conductivity type are in the well regions. The source regions and the heavy body regions are adjacent trench sidewalls, and the heavy body regions extend over the source regions along the trench sidewalls to a top surface of the mesa regions.
    Type: Application
    Filed: September 16, 2008
    Publication date: March 18, 2010
    Inventors: James Pan, Scott L. Hunt, Dean E. Probst, Hossein Paravi
  • Structure and Method for Forming a Shielded Gate Trench FET with an Inter-Electrode Dielectric Having a Nitride Layer Therein
    Publication number: 20090321817
    Abstract: A shielded gate field effect transistor (FET) comprises a plurality of trenches extending into a semiconductor region. A shield electrode is disposed in a bottom portion of each trench, and a gate electrode is disposed over the shield electrode in each trench. An inter-electrode dielectric (IED) extends between the shield electrode and the gate electrode. The IED comprises a first oxide layer and a nitride layer over the first oxide layer.
    Type: Application
    Filed: June 26, 2008
    Publication date: December 31, 2009
    Inventor: Scott L. Hunt