Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.

Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.

Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.

Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.

Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.

Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.

Abstract: The present invention discloses a method that includes: providing two wafers; forming raised contacts on the two wafers; aligning the two wafers; bringing together the raised contacts; locally deflecting the two wafers; and bonding the raised contacts. The present invention also discloses a bonded-wafer structure that includes: a first wafer, the first wafer being locally deflected, the first wafer including a first raised contact; and a second wafer, the second wafer being locally deflected, the second wafer including a second raised contact, wherein the second raised contact is bonded to the first raised contact.

Abstract: The invention provides a stacked wafer structure with decreased failures. In one embodiment, there is a barrier layer deposited on exposed surfaces of conductors that extend across a distance between first and second device structures. The barrier layer may prevent diffusion and electromigration of the conductor material, which may decrease incidences of shorts and voids in the stacked wafer structure.

Abstract: A method and article to provide a three-dimensional (3-D) IC wafer process flow. In some embodiments, the method and article include bonding a device layer of a multilayer wafer to a device layer of another multilayer wafer to form a bonded pair of device layers, each of the multilayer wafers including a layer of silicon on a layer of porous silicon (SiOPSi) on a silicon substrate where the device layer is formed in the silicon layer, separating the bonded pair of device layers from one of the silicon substrates by splitting one of the porous silicon layers, and separating the bonded pair of device layers from the remaining silicon substrate by splitting the other one of the porous silicon layers to provide a vertically stacked wafer.

Abstract: The present invention discloses a method that includes: providing two wafers; forming raised contacts on the two wafers; aligning the two wafers; bringing together the raised contacts; locally deflecting the two wafers; and bonding the raised contacts. The present invention also discloses a bonded-wafer structure that includes: a first wafer, the first wafer being locally deflected, the first wafer including a first raised contact; and a second wafer, the second wafer being locally deflected, the second wafer including a second raised contact, wherein the second raised contact is bonded to the first raised contact.

Abstract: The present invention discloses a method that includes: providing two wafers; forming raised contacts on the two wafers; aligning the two wafers; bringing together the raised contacts; locally deflecting the two wafers; and bonding the raised contacts. The present invention also discloses a bonded-wafer structure that includes: a first wafer, the first wafer being locally deflected, the first wafer including a first raised contact; and a second wafer, the second wafer being locally deflected, the second wafer including a second raised contact, wherein the second raised contact is bonded to the first raised contact.

Abstract: The invention provides a stacked wafer structure with decreased failures. In one embodiment, there is a barrier layer deposited on exposed surfaces of conductors that extend across a distance between first and second device structures. The barrier layer may prevent diffusion and electromigration of the conductor material, which may decrease incidences of shorts and voids in the stacked wafer structure.

Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.

Abstract: Embodiments of a method of bonding wafers together using a metal interlayer deposited on conductors of each wafer. Also disclosed is a wafer stack formed according to the method of wafer bonding using a metal interlayer.