Abstract: A method and apparatus is provided that combines bandgap trim, temperature sensor trim, comparator offset trim, and the setting of the temperature trip point. A comparator compares a bandgap reference voltage and temperature sensor voltage and trips the circuit when the temperature voltage is less than the bandgap reference voltage. The temperature voltage is combined with a compensating voltage to trim the circuit and set trip point. A method is provided to adjust the compensating voltage until the circuit trips at the any desired temperature.

Abstract: A segmented digital-to-analog converter circuit employs a tri-level technique to provide an output current in response to a bit code. DAC slice circuits are activated in unary fashion in response to their respective control signal, which are provided by a decoder circuit in response to the high-order bits. Each DAC slice circuit provides a binary weighted current to a summing node in response to the middle-order bits. One of the DAC slice circuits is selected to direct a portion of its total current to the input of a DAC_LOW circuit, where the input current is divided to provide a divided current to the summing node in response to the low-order bits. At certain code transitions a different DAC slice circuit is selected to provide the input current, and the previously selected DAC slice circuit redirects its total current to the summing node such that differential non-linearity errors are minimized.

Abstract: A power-on sense circuit accurately senses a power-on condition when a power supply voltage exceeds a desired trigger voltage level. The power-on sense circuit includes a voltage-to-current converter circuit and a beta-multiplier reference circuit. The voltage-to-current converter circuit and the beta-multiplier reference circuit generate currents that relate to the power supply voltage. By sensing a balanced current operating condition with the beta-multiplier reference circuit, the power-on sense circuit determines when a desired trigger voltage has been achieved. The trigger voltage level has a zero temperature coefficient at median operating temperatures, and has a slightly downward curvature shape without the need for high-current resistor-dividers or bandgap circuits. The power-on sense circuit may be adapted for use as a power-on reset signal. By adding an amplifier stage to the outputs signal, the power-on sense circuit may also be used as an analog reference voltage generator.

Abstract: An amplifier employs a first and second input stage amplifier, and an output stage amplifier for rail-to-rail operation. The rail-to-rail amplifier is driven by an input signal with a particular common-mode voltage. The first amplifier is active during a first range of common-mode voltages, while the second amplifier is active during a second range. A monitor circuit includes an input differential pair that operates at the same common-mode voltage as the first input differential pair in the first amplifier. The monitor circuit senses when the first amplifier has reached a condition where the amplifier begins to stop working by monitoring a current flowing in the input differential pair. The monitor circuit controls the bias current in the second amplifier's bias circuit such that the second amplifier is enabled when the current in the monitor circuit input differential pair drops down towards zero.

Abstract: A method and apparatus for dynamically determining when a bias circuit has reached a steady-state operation so that the memory elements (e.g., EPROMs) may be read. The bias circuit includes a read enable circuit, a bias circuit, and an output circuit. The bias circuit is configured to dynamically detect a memory element bias voltage in response to a read enable signal, which is provided by the read enable circuit. The memory element bias voltage varies from an initial voltage to a final voltage based on the amount of loading due to the memory elements (e.g., EPROMs). The bias circuit outputs a read signal when the memory element bias voltage reaches the final voltage. The memory elements initiate reading data that is stored in the memory elements in response to the read signal. The bias circuit may include a bias generator, a memory element driver and a detector. The bias generator is configured to generate an internal bias voltage.

Abstract: A preamplifier circuit couple to a magneto-resistive (MR) head used in the read circuitry of a magnetic storage device includes differential amplifiers coupled to receive an input from the MR head and to provide output signals. The preamplifier is designed to provide a low noise level. To minimize noise, transistors of the differential amplifiers provide high current gain and have large device geometries.