Abstract: A method is provided for fabricating a semiconductor device on a semiconductor substrate. A plurality of narrow gate pitch transistors (NPTs) and wide gate pitch transistors (WPTs) are formed on and in the semiconductor substrate. The NPTs are spaced apart by a first distance, and the WPTs are spaced apart by a second distance greater than the first distance. A first stress liner layer is deposited overlying the NPTs, the WPTs and the semiconductor layer, an etch stop layer is deposited overlying the first stress liner layer, and a second stress liner layer is deposited overlying the etch stop layer. A portion of the second stress liner layer which overlies the WPTs is covered, and an exposed portion of the second stress liner layer which overlies the NPTs is removed to expose an exposed portion of the etch stop layer. The exposed portion of the etch stop layer which overlies the NPTs is removed.

Abstract: According to a method for fabricating a stress enhanced MOS device having a channel region at a surface of a semiconductor substrate, first and second trenches are etched into the semiconductor substrate, the first trench having a first side surface, and the second trench having a second side surface. The first and second side surfaces are formed astride the channel region. The first and second side surfaces are then oxidized in a controlled oxidizing environment to thereby grow an oxide region. The oxide region is then removed, thereby repositioning the first and second side surfaces closer to the channel region. With the first and second side surfaces repositioned, the first and second trenches are filled with SiGe.

Abstract: A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first silicon germanium region having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate.

Abstract: An MOS device having enhanced mobility and a method for its fabrication are provided. The method comprises providing a P-type monocrystalline silicon germanium substrate having a first lattice constant and a channel region at the substrate surface, forming a gate insulator layer on the substrate, forming a gate electrode having a first sidewall and a second sidewall overlying the channel. First and second recesses are etched into the substrate in alignment with the first and the second gate electrode sidewalls, respectively. The recesses are filled by epitaxially growing a layer of embedded monocrystalline semiconductor material characterized by a second lattice constant less than the first lattice constant to impart a tensile strain on the channel region.

Abstract: Methods and a structure are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut.

Abstract: By providing a hard mask layer stack including at least three different layers for patterning a gate electrode structure, constraints demanded by sophisticated lithography, as well as cap layer integrity, in a subsequent selective epitaxial growth process may be accomplished, thereby providing the potential for further device scaling of transistor devices requiring raised drain and source regions.

Abstract: By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number of interface defects located between the grown silicon layer and the initial substrate surface may be significantly reduced. Consequently, deleterious effects such as charge carrier gettering or creating diffusion paths for dopants may be suppressed.

Abstract: A method and arrangement for reducing the series resistance of the source and drain in a MOSFET device provides for epitaxially grown regions on top of the source and drain extensions to cover portions of the top surfaces of the silicide regions formed on the substrate. The epitaxial material provides an extra flow path for current to flow through to the silicide from the extension, as well as increasing the surface area between the source/drain and the silicide to reduce the contact resistance between the source/drain and the silicide.

Abstract: The height of epitaxially grown semiconductor regions in extremely scaled semiconductor devices may be adjusted individually for different device regions in that two or more epitaxial growth steps may be carried out, wherein an epitaxial growth mask selectively suppresses the formation of a semiconductor region in a specified device region. In other embodiments, a common epitaxial growth process may be used for two or more different device regions and subsequently a selective oxidation process may be performed on selected device regions so as to precisely reduce the height of the previously epitaxially grown semiconductor regions in the selected areas.

Abstract: Integration schemes are presented which provide for decoupling the placement of deep source/drain (S/D) implants with respect to a selective epitaxial growth (SEG) raised S/D region, as well as decoupling silicide placement relative to a raised S/D feature. These integration schemes may be combined in multiple ways to permit independent control of the placement of these features for optimizing device performance. The methodology utilizes multiple spacers to decrease current crowding effects in devices due to proximity effects between LDD and deep S/D regions in reduced architecture devices.

Abstract: Methods for manufacturing an integrated circuit are provided. An exemplary method comprises the step of providing a silicon substrate having a first crystalline orientation. A silicon layer having a second crystalline orientation is bonded to the silicon substrate. The second crystalline orientation is different from the first crystalline orientation. The silicon layer is etched to expose a portion of the silicon substrate and an amorphous silicon layer is deposited on the exposed portion. The amorphous silicon layer is transformed into a regrown crystalline silicon layer having the first crystalline orientation. A first field effect transistor is formed on the silicon layer and a second field effect transistor is formed on the regrown crystalline silicon layer.

Abstract: By using sidewall spacers adjacent to a gate electrode structure both as an epitaxial growth mask and an implantation mask, the complexity of a conventional process flow for forming raised drain and source regions may be significantly reduced, thereby reducing production costs and enhancing yield by lowering the defect rate.

Abstract: By recessing a semiconductor layer, preferably by locally oxidizing the semiconductor layer, a stress-inducing material and/or a dopant species may be introduced into the thinned semiconductor layer in the vicinity of a gate electrode structure by means of a subsequent epitaxial growth process. In particular, the stress-inducing material formed adjacent to the gate electrode structure exerts compressive or tensile stress, depending on the type of material deposited, thereby also enhancing the mobility of the charge carriers in a channel region of the transistor element.

Abstract: A first gate structure and a second gate structure are formed overlying a semiconductor substrate. A first protective layer is formed overlying the first gate structure and an associate source drain region. A first epitaxial layer is formed overlying the second source drain prior to removal of the first protective layer.

Abstract: By providing a hard mask layer stack including at least three different layers for patterning a gate electrode structure, constraints demanded by sophisticated lithography, as well as cap layer integrity, in a subsequent selective epitaxial growth process may be accomplished, thereby providing the potential for further device scaling of transistor devices requiring raised drain and source regions.

Abstract: By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number of interface defects located between the grown silicon layer and the initial substrate surface may be significantly reduced. Consequently, deleterious effects such as charge carrier gettering or creating diffusion paths for dopants may be suppressed.

Abstract: An integrated circuit and methods for its manufacture are provided. The integrated circuit comprises a bulk silicon substrate having a first region of <100> crystalline orientation and a second region of <110> crystalline orientation. A layer of silicon on insulator overlies a portion of the bulk silicon substrate. At least one field effect transistor is formed in the layer of silicon on insulator, at least one P-channel field effect transistor is formed in the second region of <110> crystalline orientation, and at least one N-channel field effect transistor is formed in the first region of <100> crystalline orientation.

Abstract: Semiconductor devices with improved transistor performance are fabricated by forming a composite oxide/nitride liner under a gate electrode sidewall spacer. Embodiments include depositing a conformal oxide layer by decoupled plasma deposition, depositing a conformal nitride layer by decoupled plasma deposition, depositing a spacer layer and then etching.

Abstract: By using sidewall spacers adjacent to a gate electrode structure both as an epitaxial growth mask and an implantation mask, the complexity of a conventional process flow for forming raised drain and source regions may be significantly reduced, thereby reducing production costs and enhancing yield by lowering the defect rate.

Abstract: The height of epitaxially grown semiconductor regions in extremely scaled semiconductor devices may be adjusted individually for different device regions in that two or more epitaxial growth steps may be carried out, wherein an epitaxial growth mask selectively suppresses the formation of a semiconductor region in a specified device region. In other embodiments, a common epitaxial growth process may be used for two or more different device regions and subsequently a selective oxidation process may be performed on selected device regions so as to precisely reduce the height of the previously epitaxially grown semiconductor regions in the selected areas.