Abstract: An embodiment generates a composite high speed clock with embedded frame synchronization using simple digital encoding of a high speed reference clock. The high speed reference clock and self-aligned frame synchronization signal are recovered by standard logic gate circuitry. The encoding and decoding circuits are comprised of basic digital logic gates with low propagation delay skew and timing jitter. The encoded clock is easier to transmit from source unit to destination unit over common transmission media (i.e., digital transceivers, amplifiers, splitters, connectors and coaxial cable) because only a single interface is required and because the encoding scheme reduces the composite clock to a minimal transmission bandwidth with constrained waveform harmonic content, relative to a low frequency frame sync with fast rise time that requires a broadband transmission media.

Abstract: A satellite communication system which performs multicast switching on data cells. A switch 80 receives the data cells at a set of input ports IP1 and directs those including a multicast routing code to a first set of output ports OP2 or OP128. The switch 80 also directs data cells effectively omitting the multicast routing code to a second set of output ports OP1. One or more multicast replication modules 110, 130 are coupled to the first set of output ports and replicate data cells requiring multicast processing. During the processing, the multicast routing code is effectively omitted and the replicated cells are coupled to input ports IP2 or IP 128 so that the replicated data cells are transmitted to the second set of output ports OP1. An outbound processing module 100 is coupled to output ports OP1 for processing the data cells for transmission over a satellite downlink transmitter 104.

Abstract: The present invention is a method and apparatus for processing data packets in the outbound module of a space-based cell switch. The present invention uses an expanded set of queuing parameters to determine an output queue in which to store each data packet. The method includes the steps of selecting an expanded set of queuing parameters (202), establishing several output queues (204) based on combinations of the expanded set of queuing parameters, receiving data packets in a communications uplink (206), examining the header portion of each received data packet (208, 210 and 212), determining an appropriate output queue in which to store the data packet (214 and 216), and switching the received data packets to that appropriate output queue (218). The present apparatus includes several input modules (102), a switch control output (114) connected between the input module (102) and a switch fabric (104), and a several output modules (106) connected to the switch fabric (104).

Abstract: The method allocates (302) subclass entries in an ordered list (200) (which may be organized as a table, for example). Each entry (210-214) generally corresponds to one of several predetermined cell subclasses, and the allocation reserves a total number of each subclass entry in the ordered list according to a predetermined amount of bandwidth desired for each cell subclass. The subclasses may be associated with factors such as coding rate, downlink beam area, virtual paths or virtual circuits, quality of service parameters, and the like. The method then examines (304) each subclass entry in the ordered list and selects (306) a cell from a cell memory (which may be a queue) that matches the subclass entry. The matched cell is then transmitted (308). The method may also allocate sets of subclass entries in groups corresponding to a frame size and dynamically update (310) the ordered list during operation of the cell switch.

Abstract: A satellite communication system which performs switching on data cells. A switch (80) receives the data cells at a set of input ports (IP1-IP128) and directs them to a set of output ports (OP1-OP128). In order to arbitrate input data cells contending for the same output port, decision factor codes and routing codes are serially conducted to input registers (210), and a pseudo-random sequence code is appended. The combined codes are ordered by routing code in a decoder (220). The code with the highest decision factor code is selected in one or more determinators (230 and 240). The selected code is identified by a bit in a result register (250).