Abstract: Systems, computer program products and/or computer-implemented methods described herein relate to a quantum control system architecture for real-time Pauli twirling of quantum programs. A system can include a memory that stores computer executable components and a processor that executes the computer executable components, which can include an initialization component that determines a seed to be applied to a first pseudorandom number generator (PRNG) associated with a first qubit of an input quantum circuit, the seed being shared with one or more second PRNGs associated with respective second qubits of the input quantum circuit that share a frame with the first qubit; and a Pauli twirling component that applies selected Clifford operations to the first qubit before and after execution of respective layers of the input quantum circuit, where the selected Clifford operations are selected according to an output of the first PRNG that is produced based on the seed.

Abstract: Systems, computer program products and/or computer-implemented methods described herein relate to a quantum control system architecture with low-latency unstructured control-flow, e.g., including gapless waveform playback through remote invocation of control subsequences. A system can include a memory that stores computer executable components and a processor that executes the computer executable components, which can include an orchestration component that determines selected real-time control sequences for synchronized execution by qubit controllers and a synchronization component that communicates a control message to the qubit controllers, where the control message causes the qubit controllers to wait until a common action time and to execute the selected real-time control sequences at the common action time.

Abstract: One or more systems, devices, computer program products and/or computer-implemented methods of use provided herein relate to a process to rapidly generate waveforms for quantum operations, the process employing separation of waveform software control from waveform generation control. An exemplary wave player system can comprise a waveform generator, a memory associated with the waveform generator, wherein the memory stores a waveform play table comprising a plurality of play table entries having a plurality of waveform definition aspects that comprise, or direct to, a plurality of parameters that define a plurality of waveforms, and a processing unit associated with the waveform generator, wherein the processing unit accesses a first play table entry, of the plurality of play table entries, comprising a first waveform definition aspect, of the plurality of waveform definition aspects, based on an instruction obtained at the processing unit.

Abstract: Systems, compute-implemented methods, and computer program products to facilitate automated waveform validation are provided. According to an embodiment, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components comprise a waveform comparison component that compares a digital conversion of an analog signal to a reference signal.

Abstract: Systems, compute-implemented methods, and computer program products to facilitate automated waveform validation are provided. According to an embodiment, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components comprise a waveform comparison component that compares a digital conversion of an analog signal to a reference signal.

Abstract: A processor core of a data processing system, in response to a first instruction, generates a copy-type request specifying a source real address and transmits it to a lower level cache. In response to a second instruction, the processor core generates a paste-type request specifying a destination real address associated with a memory-mapped device and transmits it to the lower level cache. In response to the copy-type request, the lower level cache copies a data granule from a storage location specified by the source real address into a non-architected buffer. In response to the paste-type request, the lower level cache writes the data granule from the non-architected buffer to the memory-mapped device. In response to receipt of the data granule, the memory-mapped device stores the data granule in a queue in the system memory associated with a hardware device of the data processing system.

Abstract: A processor core of a data processing system, in response to a first instruction, generates a copy-type request specifying a source real address and transmits it to a lower level cache. In response to a second instruction, the processor core generates a paste-type request specifying a destination real address associated with a memory-mapped device and transmits it to the lower level cache. In response to the copy-type request, the lower level cache copies a data granule from a storage location specified by the source real address into a non-architected buffer. In response to the paste-type request, the lower level cache writes the data granule from the non-architected buffer to the memory-mapped device. In response to receipt of the data granule, the memory-mapped device stores the data granule in a queue in the system memory associated with a hardware device of the data processing system.

Abstract: A verification environment enables verification of runtime switch-over—i.e., a switch-over without restarting the device under test—between multiple I/O protocols that share a same physical interface. The device under test can be a switch unit having multiple logical protocol processing units and a logical protocol multiplexor. The verification environment includes a switch-over detector which monitors the state of the device under test, and a switch-over controller that controls the switch-over sequence by pausing and re-starting traffic on all or specific protocol drivers of the verification environment.

Abstract: A verification environment enables verification of runtime switch-over—i.e., a switch-over without restarting the device under test—between multiple I/O protocols that share a same physical interface. The device under test can be a switch unit having multiple logical protocol processing units and a logical protocol multiplexor. The verification environment includes a switch-over detector which monitors the state of the device under test, and a switch-over controller that controls the switch-over sequence by pausing and re-starting traffic on all or specific protocol drivers of the verification environment.

Abstract: Embodiments herein describe a switchboard coupled to a system bus in an integrated circuit for managing the flow of data between different entities coupled to the bus (e.g., processing cores, accelerators, memory controllers, input/output (I/O) interfaces, and the like). The switchboard is a hardware module that may be tasked with assigning different system bus addresses (or range of addresses) to each of the entities coupled to the bus. These addresses may be unique such that each entity can be uniquely identified by its assigned address. The address space of the system bus also includes managed address that are reserved—i.e., are not assigned to any particular entity. The switchboard is tasked with assigning the managed addresses (also referred to as virtual channels) to an entity which can be used to enable direct communication between hardware entities using the system bus.

Abstract: A verification environment enables verification of runtime switch-over—i.e., a switch-over without restarting the device under test—between multiple I/O protocols that share a same physical interface. The device under test can be a switch unit having multiple logical protocol processing units and a logical protocol multiplexor. The verification environment includes a switch-over detector which monitors the state of the device under test, and a switch-over controller that controls the switch-over sequence by pausing and re-starting traffic on all or specific protocol drivers of the verification environment.

Abstract: A verification environment enables verification of runtime switch-over—i.e., a switch-over without restarting the device under test—between multiple I/O protocols that share a same physical interface. The device under test can be a switch unit having multiple logical protocol processing units and a logical protocol multiplexor. The verification environment includes a switch-over detector which monitors the state of the device under test, and a switch-over controller that controls the switch-over sequence by pausing and re-starting traffic on all or specific protocol drivers of the verification environment.

Abstract: A system is disclosed for concurrently processing order sensitive data packets. A first data packet from a plurality of sequentially ordered data packets is directed to a first offload engine. A second data packet from the plurality of sequentially ordered data packets is directed to a second offload engine, wherein the second data packet is sequentially subsequent to the first data packet. The second offload engine receives information from the first offload engine, wherein the information reflects that the first offload engine is processing the first data packet. Based on the information received at the second offload engine, the second offload engine processes the second data packet so that critical events in the processing of the first data packet by the first offload engine occur prior to critical events in the processing of the second data packet by the second offload engine.

Abstract: A system is disclosed for fetching control instructions for a direct memory access (DMA) engine shared between a plurality of threads. For a data transfer from a first thread by a DMA engine, the DMA engine fetches and processes a predetermined number of control instructions (or work queue elements) for the data transfer, each of the control instructions including an amount and location of data to transfer. The DMA engine determines a total amount of data transferred as a result of the data transfer. The DMA engine then determines a difference between the total amount of data transferred and a threshold amount of data, wherein the threshold amount of data indicates a preferred amount of data to be transferred for the first thread. The predetermined number of control instructions to fetch is updated based on the determined difference.

Abstract: A system is disclosed for fetching control instructions for a direct memory access (DMA) engine shared between a plurality of threads. For a data transfer from a first thread by a DMA engine, the DMA engine fetches and processes a predetermined number of control instructions (or work queue elements) for the data transfer, each of the control instructions including an amount and location of data to transfer. The DMA engine determines a total amount of data transferred as a result of the data transfer. The DMA engine then determines a difference between the total amount of data transferred and a threshold amount of data, wherein the threshold amount of data indicates a preferred amount of data to be transferred for the first thread. The predetermined number of control instructions to fetch is updated based on the determined difference.

Abstract: A system is disclosed for concurrently processing order sensitive data packets. A first data packet from a plurality of sequentially ordered data packets is directed to a first offload engine. A second data packet from the plurality of sequentially ordered data packets is directed to a second offload engine, wherein the second data packet is sequentially subsequent to the first data packet. The second offload engine receives information from the first offload engine, wherein the information reflects that the first offload engine is processing the first data packet. Based on the information received at the second offload engine, the second offload engine processes the second data packet so that critical events in the processing of the first data packet by the first offload engine occur prior to critical events in the processing of the second data packet by the second offload engine.

Abstract: A method for designing integrated circuits uses clock signal interleaving to reduce the likelihood of a soft error arising from an upset in a clock distribution network. At least two circuits in a circuit description are identified as being sensitive to radiation, and different clock distribution nodes are assigned to the two circuits. Several exemplary implementations are disclosed. The second circuit may be a redundant replica of the first circuit, such as a reset circuit. The first and second circuits may be components of a modular redundant circuit such as a triple modular redundancy flip-flop. The first circuit may include a set of data bits for an entry of a storage array such as a register or memory array, and the second circuit may include a set of check bits associated with the entry.

Abstract: A method of speculative credit data flow control includes defining a low watermark value as a function of a number of open buffers in a receiving unit; receiving a data packet from a sending unit; determining whether the data packet includes a packet delay indicator; defining a first speculative credit value responsive to receiving the packet delay indicator; defining a second speculative credit value as a function of the first speculative credit value added to a regular credit value; generating a flow control packet including the second speculative credit value; and sending the flow control packet to the sending unit.

Abstract: A method of designing a layout of an integrated circuit for increased radiation tolerance by ensuring that any critical components (those deemed particularly sensitive to radiation-induced soft errors) are at spacings greater than a predetermined threshold based on particle migration within the silicon substrate. The method starts with an initial placement, identifies the objects for which radiation tolerance is desired, determines whether any of those objects and, if so, moves the relevant objects to increase the spacing. An exemplary threshold for contemporary CMOS device technologies is 5 ?m. The objects can be moved by vertically and/or horizontally shifting away from a reference point of the integrated circuit. The critical objects may include triplicated (redundant) structures, clock control latches, or a reset bit. The method can be used in conjunction with other placement optimizations such as area, power and timing.

Abstract: A method of speculative credit data flow control includes defining a low watermark value as a function of a number of open buffers in a receiving unit; receiving a data packet from a sending unit; determining whether the data packet includes a packet delay indicator; defining a first speculative credit value responsive to receiving the packet delay indicator; defining a second speculative credit value as a function of the first speculative credit value added to a regular credit value; generating a flow control packet including the second speculative credit value; and sending the flow control packet to the sending unit.