Abstract: Cleaning a recording head slider in-drive during operation is accomplished by periodically performing a series of full stroke seek operations, whereby liquid contaminants that may have migrated to the head slider are flung from the slider and liquid from the disk surface may be adsorbed onto the slider for removal by way of flinging. Consequently, head-disk spacing may be stabilized and data write operations improved. Furthermore, the series of full stroke seek operations may be performed at predetermined intervals, and for a predetermined period of time. However, the series may be interrupted by a client request, and continued thereafter, so as not to affect the operational status of the recording system.

Abstract: Cleaning a recording head slider in-drive during operation is accomplished by periodically performing a series of full stroke seek operations, whereby liquid contaminants that may have migrated to the head slider are flung from the slider and liquid from the disk surface may be adsorbed onto the slider for removal by way of flinging. Consequently, head-disk spacing may be stabilized and data write operations improved. Furthermore, the series of full stroke seek operations may be performed at predetermined intervals, and for a predetermined period of time. However, the series may be interrupted by a client request, and continued thereafter, so as not to affect the operational status of the recording system.

Abstract: A redundant clock switch circuit that includes two delay circuits and control logic is presented. The first delay circuit is configured to delay a first clock signal to produce a first delayed clock signal, while the second delay circuit is configured to delay a second clock signal to produce a second delayed clock signal. The control logic is configured to control the delay circuits to maintain phase alignment between the first and second delayed clock signals. The control logic is also configured to select one of the first and second delayed clock signals as an output clock signal.

Abstract: A system comprises a primary oscillator that provides a first signal having a first phase and a backup oscillator that provides a second signal having a second phase. The system also comprises trim logic coupled to the backup oscillator logic. Prior to failure of the primary oscillator, the trim logic adjusts the second phase to match the first phase. Upon failure of the primary oscillator, the second signal is used in lieu of the first signal.

Abstract: Phase-locked loop (PLL) logic comprises an oscillator that produces a first oscillator signal and phase detect logic that determines a phase difference between the first oscillator signal and a second oscillator signal. After the second oscillator signal is replaced by a third oscillator signal, the phase detect logic determines another phase difference between the first oscillator signal and the third oscillator signal. The PLL removes the phase difference from the another phase difference to produce an intermediate signal. The oscillator adjusts the first oscillator signal using the intermediate signal.

Abstract: A system comprises a primary oscillator that provides a first signal having a first phase and a backup oscillator that provides a second signal having a second phase. The system also comprises trim logic coupled to the backup oscillator logic. Prior to failure of the primary oscillator, the trim logic adjusts the second phase to match the first phase. Upon failure of the primary oscillator, the second signal is used in lieu of the first signal.

Abstract: Phase-locked loop (PLL) logic comprises an oscillator that produces a first oscillator signal and phase detect logic that determines a phase difference between the first oscillator signal and a second oscillator signal. After the second oscillator signal is replaced by a third oscillator signal, the phase detect logic determines another phase difference between the first oscillator signal and the third oscillator signal. The PLL removes the phase difference from the another phase difference to produce an intermediate signal. The oscillator adjusts the first oscillator signal using the intermediate signal.

Abstract: A redundant clock switch circuit that includes two delay circuits and control logic is presented. The first delay circuit is configured to delay a first clock signal to produce a first delayed clock signal, while the second delay circuit is configured to delay a second clock signal to produce a second delayed clock signal. The control logic is configured to control the delay circuits to maintain phase alignment between the first and second delayed clock signals. The control logic is also configured to select one of the first and second delayed clock signals as an output clock signal.

Abstract: An enclosure is disclosed. The enclosure comprises a chassis having a plurality of slots configured to hold a plurality of blades. At least one wet heat sink is positioned adjacent to each of the plurality of slots. An input piping system is coupled to the wet heat sinks and configured to supply cooling fluid to each of the wet heat sinks. An exhaust piping system is also coupled to the wet heat sinks and configured to remove the cooling fluid from the wet heat sinks. At least one blade is installed into one of the slots. The blade has at least one dry heat sink attached to the blade. The at least one dry heat sink is in thermal contact with the at least one wet heat sink positioned adjacent to the first slot.

Abstract: A method and apparatus for regulating the concentration of a vapor within a hard drive are provided. In one embodiment, the method may include providing a source chemical of a vapor in a first cavity formed within a first object, providing an absorptive chemical which absorbs the vapor in a second cavity formed within the first object, and providing a third cavity formed by a hard drive housing of the hard drive. A first conductance path having a first conductance connects the first cavity to the third cavity, a second conductance path having a second conductance connects the second cavity to the third cavity, and the first conductance and the second conductance maintain a partial pressure level of the vapor within the third cavity.

Abstract: A method and apparatus for regulating the concentration of a vapor within a hard drive are provided. In one embodiment, the method may include providing a source chemical of a vapor in a first cavity formed within a first object, providing an absorptive chemical which absorbs the vapor in a second cavity formed within the first object, and providing a third cavity formed by a hard drive housing of the hard drive. A first conductance path having a first conductance connects the first cavity to the third cavity, a second conductance path having a second conductance connects the second cavity to the third cavity, and the first conductance and the second conductance maintain a partial pressure level of the vapor within the third cavity.

Abstract: The invention includes a method of debugging an embedded processor. Scratch pad memory of an embedded processor is accessed to form a configuration file characterizing the configuration of scratch pad regions of the scratch pad memory. The embedded processor is debugged using information from the configuration file. The invention also includes an embedded processor with a processor core and scratch pad memory connected to the processor core. The scratch pad memory includes a set of scratch pad regions. The scratch pad memory stores values characterizing base addresses and region size values of the set of scratch pad regions.

Abstract: A method and apparatus are disclosed for automating the task of adding video content to a video server. Instructions implemented in the video server cause the video server to automatically examine each new file added to the server to determine whether the new file contains a video program. If the new file contains a video program, the video server examines the data structure of the new file to determine the format used to encode the video program. The video server attaches an indication of the encoding format to the video program and adds the video program to a list of video content available to users having access to the video server. The video server is disclosed as accessible from a client computer over an IP network, although other arrangements are possible.