Patents by Inventor Scott Muma

Scott Muma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12192079
    Abstract: A method and apparatus in which a data stream is received that includes constant bit rate (CBR) carrier streams, at least one of which comprises frames, a cumulative phase offset report (CPOR) and a client rate report (CRR). A counter accumulating a PHY-scaled stream clock (IPSCk) is sampled at a nominal sampling period (Tps) to obtain a cumulative PHY-scaled count (CPSC). A PHY-scaled stream phase offset (PSPO) is calculated that indicates phase difference between PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD). The data stream is demultiplexed to obtain CBR carrier streams. Respective CBR carrier streams include a previous network node CPOR (CPOR-P) and a previous network node CPO (CPO-P). A CPO is calculated that is a function of CPO-P and PSPO. CPO-P is replaced with the calculated CPO. The CBR carrier streams are multiplexed into intermediate-network-node data streams that are transmitted from the intermediate-network-node.
    Type: Grant
    Filed: May 27, 2023
    Date of Patent: January 7, 2025
    Assignee: Microchip Technology Inc.
    Inventors: Scott Muma, Winston Mok, Steven Scott Gorshe
  • Patent number: 11799626
    Abstract: A method and apparatus in which a data stream generated by a previous network node, a cumulative phase offset report (CPOR) and a client rate report (CRR) are received. A counter accumulating a PHY-scaled stream clock (IPSCk) is sampled at a nominal sampling period (Tps) to obtain a cumulative PHY-scaled count (CPSC). A PHY-scaled stream phase offset (PSPO) is calculated that indicates phase difference between a PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD), where IPSD indicates CPSC increment between successive CPSC samples. The data stream is demultiplexed to obtain CBR carrier streams that include a previous network node CPOR (CPOR-P) and a previous network node CPO (CPO-P). A CPO is calculated that is a function of CPO-P and the PSPO. CPO-P is replaced with the calculated CPO. The CBR carrier streams are multiplexed into intermediate-network-node data streams that are transmitted from the intermediate-network-node.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: October 24, 2023
    Assignee: Microchip Technology Inc.
    Inventors: Scott Muma, Winston Mok, Steven Scott Gorshe
  • Publication number: 20230300047
    Abstract: A method and apparatus in which a data stream is received that includes constant bit rate (CBR) carrier streams, at least one of which comprises frames, a cumulative phase offset report (CPOR) and a client rate report (CRR). A counter accumulating a PHY-scaled stream clock (IPSCk) is sampled at a nominal sampling period (Tps) to obtain a cumulative PHY-scaled count (CPSC). A PHY-scaled stream phase offset (PSPO) is calculated that indicates phase difference between PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD). The data stream is demultiplexed to obtain CBR carrier streams. Respective CBR carrier streams include a previous network node CPOR (CPOR-P) and a previous network node CPO (CPO-P). A CPO is calculated that is a function of CPO-P and PSPO. CPO-P is replaced with the calculated CPO. The CBR carrier streams are multiplexed into intermediate-network-node data streams that are transmitted from the intermediate-network-node.
    Type: Application
    Filed: May 27, 2023
    Publication date: September 21, 2023
    Applicant: Microchip Technology Inc.
    Inventors: Scott Muma, Winston Mok, Steven Scott GORSHE
  • Patent number: 9824773
    Abstract: The voltage applied to an integrated circuit is scaled so as to account for variations in the manufacturing processes, temperature, and the like, and to allow for power/performance optimization of the integrated circuit. The integrated circuit may characterized during a manufacturing test or anytime thereafter. The characterization data, which reflects the performance and power consumption of the integrated circuit, is used to determine an associated processing/speed bin, which in turn, defines the voltage that will be applied to the integrated circuit during normal operation. Optionally, a number of different supply voltages are applied to different circuit blocks disposed in the same integrated circuit. Each such circuit block may have a different characterization data associated with a different supply voltage.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: November 21, 2017
    Assignee: MICROSEMI STORAGE SOLUTIONS, INC.
    Inventors: Karim Arabi, Scott Muma, Nick Rolheiser, Norbert Diesing
  • Patent number: 8854963
    Abstract: Methods and systems are provided for controlling elements in a signal path of a communication network to accommodate changes in the rate of a client signal. In particular, during the bandwidth resizing (BWR) portion of ITU-T Recommendation G.7044 Hitless Adjustment of ODUflex(GFP) protocol (HAO), the nodes in the chain along the ODUflex(GFP) signal path change their output rates in parallel such that FIFO over/underflow is avoided in the nodes. Certain embodiments provide mechanisms to synchronize and stabilize the nodes in a verifiable manner.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: October 7, 2014
    Assignee: PMC-Sierra US, Inc.
    Inventors: Scott Muma, Winston Ki-Cheong Mok, Steven Scott Gorshe, Karl Scheffer
  • Patent number: 7668210
    Abstract: A method and apparatus are provided for reducing current demand variations in large fanout trees. The fanout tree is split into at least 2 sub-groups, each preferably with substantially equal parasitic capacitance. Data is then scrambled according to a scrambling sequence function to provide scrambled data having a constant number of bits that are toggled with respect to time, such as when observed in pairs of sub-groups. Functionally, an apparatus according to an embodiment of the present invention includes 3 blocks: a scrambler, egress logic, and a de-scrambler. The egress logic is simply a block of storage that can reorder the bytes received from the scrambler. The de-scrambler de-scrambles the retransmitted data based on the scrambling sequence function. Embodiments of the present invention can be applied to any system where data must fanout from a single source to many destinations, such as switches.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: February 23, 2010
    Assignee: PMC-Sierra, Inc.
    Inventors: Winston Ki-Cheong Mok, Scott A. Muma, Nicholas W. Rolheiser
  • Publication number: 20050025195
    Abstract: A data detection system includes, in part, a CID detector, a DC balance monitor and a transition density detector. The CID detector is configured to detect whether the received data stream includes a CID exceeding a predetermined threshold count. The DC balance monitor is configured to detect DC imbalances in the incoming data and that may be indicative of errors in the data. The transition density detector is configured to detect whether a minimum transition density exists during a given time period. If a violation is detected by any one of these three detectors, an out-of-frame signal is asserted. The incoming data stream may be a scrambled SONET or SDH data stream.
    Type: Application
    Filed: June 2, 2004
    Publication date: February 3, 2005
    Applicant: PMC-Sierra, Inc.
    Inventors: Ian Barrett, Gregory Erker, Michael Smith, Scott Muma, Jeffrey Roe, Bernard Guay