Abstract: Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode control signal to couple the input/output terminals to either a command bus or an input/output bus. A latch in the memory device latches the command signals when the mode control signal causes the input/output terminals to be coupled to the input/output bus. As a result, the command signals continue to be applied to the command bus. When the mode control signal causes the input/output terminals to be coupled to the input/output bus, write data signals are clocked into the memory device and read data signals are clocked out of the memory device responsive to a received clock signal.

Abstract: Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode control signal to couple the input/output terminals to either a command bus or an input/output bus. A latch in the memory device latches the command signals when the mode control signal causes the input/output terminals to be coupled to the input/output bus. As a result, the command signals continue to be applied to the command bus. When the mode control signal causes the input/output terminals to be coupled to the input/output bus, write data signals are clocked into the memory device and read data signals are clocked out of the memory device responsive to a received clock signal.

Abstract: A memory block of a memory device is tested by programming a plurality of pages of the memory block, passing the memory block if a number of pages, each programmed in a first programming time, is greater than or equal to a first predetermined number and a number of pages, each programmed in a second programming time, is less than or equal to a second predetermined number, and failing the memory block if a programming time of any one of the pages exceeds a predetermined programming time or if the number of pages programmed in the first programming time is less than the first predetermined number or if the number of pages programmed in the second programming time exceeds the second predetermined number.

Abstract: An I/O compression apparatus, for testing a memory array and/or a logic circuit, is comprised of a selectable compression circuit that outputs compressed test data from the memory array/logic circuit. An I/O scan register is coupled to each I/O pad for converting serial data to parallel and parallel data to serial in response to a test mode select signal, a test data input, and a test clock.

Abstract: An I/O compression apparatus, for testing a memory array and/or a logic circuit, is comprised of a selectable compression circuit that outputs compressed test data from the memory array/logic circuit. An I/O scan register is coupled to each I/O pad for converting serial data to parallel and parallel data to serial in response to a test mode select signal, a test data input, and a test clock.

Abstract: An I/O compression apparatus, for testing a memory array and/or a logic circuit, is comprised of a selectable compression circuit that outputs compressed test data from the memory array/logic circuit. An I/O scan register is coupled to each I/O pad for converting serial data to parallel and parallel data to serial in response to a test mode select signal, a test data input, and a test clock.

Abstract: A memory block of a memory device is tested by programming a plurality of pages of the memory block, passing the memory block if a number of pages, each programmed in a first programming time, is greater than or equal to a first predetermined number and a number of pages, each programmed in a second programming time, is less than or equal to a second predetermined number, and failing the memory block if a programming time of any one of the pages exceeds a predetermined programming time or if the number of pages programmed in the first programming time is less than the first predetermined number or if the number of pages programmed in the second programming time exceeds the second predetermined number.

Abstract: A plurality of memory devices can be erase block tagged in parallel by issuing an erase pulse to memory devices that do not have memory blocks with erase block latches that indicate the block is erased. The status of the memory block is read after the erase pulse. If there are blocks remaining to be erased, erase block tag patterns are generated. Each memory block at a particular sector address has a unique erase block tag pattern to set the erase block latch for that particular memory block. The patterns are transmitted in parallel to the memory devices in a data burst.

Abstract: A memory device is tested by programming a plurality of pages of a memory block of the memory device, determining a programming time for each page, determining a total programming time for the memory block, passing the memory block if the total programming time for the memory block is less than or equal to a first predetermined time, and failing the memory block if the total programming time for the memory block exceeds the first predetermined time or the programming time for any one of the pages exceeds a second predetermined time.

Abstract: Methods and structures are described to provide trims for die on a wafer. The trims are set on a die-by-die basis instead of a wafer basis. Accordingly, the individual die are more finely tuned and more die operate at the target specifications so that yield is increased. In an embodiment, the odd and even blocks of each non volatile memory die are erased and then programmed to test the program time. Statistical analysis of the tested program times is performed. Based on this analysis the trim values are determined and programmed into the die. Accordingly, each die on a wafer has its individual trim settings.

Abstract: An I/O compression apparatus, for testing a memory array and/or a logic circuit, is comprised of a selectable compression circuit that outputs compressed test data from the memory array/logic circuit. An I/O scan register is coupled to each I/O pad for converting serial data to parallel and parallel data to serial in response to a test mode select signal, a test data input, and a test clock.

Abstract: A method of testing, polling and trimming memory pages in different memory banks simultaneously is presented, using a cache memory located in each one of the memory banks. The cache memory is at least as large as the individual memory pages and is used to record the programming voltage required to obtain the specified programming speed as well as the location of defective memory elements. A local on chip state machine may be used to accelerate the programming rate, and there may be a state machine per memory bank. With such an arrangement, the amount of testing time at wafer probe and final packaged device test may be reduced up to 40%, depending upon the number of memory pages tested in parallel.

Abstract: A method of testing, polling and trimming memory pages in different memory banks simultaneously is presented, using a cache memory located in each one of the memory banks. The cache memory is at least as large as the individual memory pages and is used to record the programming voltage required to obtain the specified programming speed as well as the location of defective memory elements. A local on chip state machine may be used to accelerate the programming rate, and there may be a state machine per memory bank. With such an arrangement, the amount of testing time at wafer probe and final packaged device test may be reduced up to 40%, depending upon the number of memory pages tested in parallel.

Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

Abstract: A plurality of memory devices can be erase block tagged in parallel by issuing an erase pulse to memory devices that do not have memory blocks with erase block latches that indicate the block is erased. The status of the memory block is read after the erase pulse. If there are blocks remaining to be erased, erase block tag patterns are generated. Each memory block at a particular sector address has a unique erase block tag pattern to set the erase block latch for that particular memory block. The patterns are transmitted in parallel to the memory devices in a data burst.

Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

Abstract: A method and apparatus for programming programmable elements of a plurality of memory devices in parallel. Each of the memory devices include an address latch for latching an address corresponding to a programmable element to be programmed and logic circuitry for receiving address load commands. The logic circuitry provides control signals to the address latch in response to receiving the load commands to cause the address latch to latch an corresponding to a programmable element to be programmed. By using the address latch and logic circuitry, the programming of a programmable element of a first memory device and the programming the second programmable element of a second memory device can occur in parallel.

Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.