Patents by Inventor Scott Notch
Scott Notch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12785852Abstract: Systems and techniques for are described herein. An optical signal is received and the optical signal is converted into an electrical signal. The electrical signal is amplified through a trans-impedance amplifier to produce an amplified signal. The amplified signal is normalized using a limit amplifier to generate a normalized signal. Bit values are determined from the normalized signal and a corresponding probability bit is generated for each bit value using a threshold detector. The bit values and the corresponding probability bit are encoded into a four-level pulse-amplitude modulation (PAM-4) signal. The PAM-4 signal is transmitted to an application-specific integrated circuit (ASIC) for data recovery and error correction processing.Type: GrantFiled: May 2, 2024Date of Patent: November 3, 2026Assignee: Calix, Inc.Inventors: Christopher Thomas Bernard, Scott Notch, Dylan Ethen
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Patent number: 12756460Abstract: A system includes one or more memories, and model generation circuitry coupled to the one or more memories, wherein the model generation circuitry is configured to: determine a plurality of decision trees, wherein each decision tree is associated with a corresponding network whose attribute data, including interface statistics, is used for training a trained model and includes one or more decision nodes for indicating whether the corresponding network includes a rogue network device; aggregate the plurality of decision trees to generate the trained model; and output the trained model for rogue network device detection.Type: GrantFiled: September 10, 2024Date of Patent: October 6, 2026Assignee: Calix, Inc.Inventors: Scott Notch, Marta Seda, Dylan Ethen, Scott Moen, Christopher T. Bernard
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Publication number: 20260128815Abstract: Systems and techniques for are described herein. A data payload is received. Parity data is removed from the data payload to generate a codeword dataset. Frames are identified in the codeword dataset. Headers of the frames are evaluated using a conditional decoding map. The frames are marked based on a destination in the headers found in the conditional decoding map. A set of target codewords are identified from the frames based on the marking. Remaining frames of the frames outside the set of target codewords are discarded. The set of target codewords is transmitted to a buffer of a conditional decoder. Codewords from the buffer are decoded using the conditional decoder.Type: ApplicationFiled: March 14, 2025Publication date: May 7, 2026Inventors: Christopher Thomas Bernard, Scott Notch
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Publication number: 20250343623Abstract: Systems and techniques for are described herein. An optical signal is received and the optical signal is converted into an electrical signal. The electrical signal is amplified through a trans-impedance amplifier to produce an amplified signal. The amplified signal is normalized using a limit amplifier to generate a normalized signal. Bit values are determined from the normalized signal and a corresponding probability bit is generated for each bit value using a threshold detector. The bit values and the corresponding probability bit are encoded into a four-level pulse-amplitude modulation (PAM-4) signal. The PAM-4 signal is transmitted to an application-specific integrated circuit (ASIC) for data recovery and error correction processing.Type: ApplicationFiled: May 2, 2024Publication date: November 6, 2025Inventors: Christopher Thomas Bernard, Scott Notch, Dylan Ethen
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Publication number: 20250202621Abstract: Systems and techniques for forward error correction decode processing power reduction are described herein. A capacity of a network slice is determined for a user network interface (UNI) based on a subset of forward error correction (FEC) codewords to be decoded by the media access control processor. A number of decoder cores is calculated to decode the capacity of the network slice. A utilization value is determined for a decoder core. A decoder utilization value is calculated for the decoder cores using the utilization value a number of decoding iterations. A non-decoding media access control processor utilization value is obtained for the network slice. A geometry is calculated for the media access control processor using the number of decoder cores, the decoder utilization value, and the non-decoding media access control processor utilization value. A media access control processor manufacturing specification data is generated based on the calculated geometry.Type: ApplicationFiled: March 5, 2025Publication date: June 19, 2025Inventors: Christopher Thomas Bernard, Scott Notch
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Publication number: 20250119239Abstract: Systems and techniques for forward error correction decode processing power reduction are described herein. A capacity of a network slice is determined for a user network interface (UNI) based on a subset of forward error correction (FEC) codewords to be decoded by the media access control processor. A number of decoder cores is calculated to decode the capacity of the network slice. A utilization value is determined for a decoder core. A decoder utilization value is calculated for the decoder cores using the utilization value a number of decoding iterations. A non-decoding media access control processor utilization value is obtained for the network slice. A geometry is calculated for the media access control processor using the number of decoder cores, the decoder utilization value, and the non-decoding media access control processor utilization value. A media access control processor manufacturing specification data is generated based on the calculated geometry.Type: ApplicationFiled: December 29, 2023Publication date: April 10, 2025Inventors: Christopher Thomas Bernard, Scott Notch
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Patent number: 12273196Abstract: Systems and techniques for forward error correction decode processing power reduction are described herein. A capacity of a network slice is determined for a user network interface (UNI) based on a subset of forward error correction (FEC) codewords to be decoded by the media access control processor. A number of decoder cores is calculated to decode the capacity of the network slice. A utilization value is determined for a decoder core. A decoder utilization value is calculated for the decoder cores using the utilization value a number of decoding iterations. A non-decoding media access control processor utilization value is obtained for the network slice. A geometry is calculated for the media access control processor using the number of decoder cores, the decoder utilization value, and the non-decoding media access control processor utilization value. A media access control processor manufacturing specification data is generated based on the calculated geometry.Type: GrantFiled: December 29, 2023Date of Patent: April 8, 2025Assignee: Calix, Inc.Inventors: Christopher Thomas Bernard, Scott Notch
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Publication number: 20250088308Abstract: Systems and techniques for forward error correction decode processing power reduction are described herein. A first codeword is identified in a network transmission. A conditional decoding window is generated that begins with the first codeword. The conditional decoding window is aligned with a frame of the network transmission. A report is generated that includes an indication of relevance of the conditional decoding window to a network device. The conditional decoding window and the report are transmitted to the network device. A conditional decoding window is received that includes a first codeword. The first codeword is decoded to determine a second codeword. A report is obtained that includes a codeword relevance bit for the second codeword. Upon a determination that the codeword relevance bit indicates that the second codeword is irrelevant, the second codeword is discarded without decoding the second codeword.Type: ApplicationFiled: September 16, 2024Publication date: March 13, 2025Inventors: Christopher Thomas Bernard, Scott Notch
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Patent number: 12095556Abstract: Systems and techniques for forward error correction decode processing power reduction are described herein. A first codeword is identified in a network transmission. A conditional decoding window is generated that begins with the first codeword. The conditional decoding window is aligned with a frame of the network transmission. A report is generated that includes an indication of relevance of the conditional decoding window to a network device. The conditional decoding window and the report are transmitted to the network device. A conditional decoding window is received that includes a first codeword. The first codeword is decoded to determine a second codeword. A report is obtained that includes a codeword relevance bit for the second codeword. Upon a determination that the codeword relevance bit indicates that the second codeword is irrelevant, the second codeword is discarded without decoding the second codeword.Type: GrantFiled: January 11, 2023Date of Patent: September 17, 2024Assignee: Calix, IncInventors: Christopher Thomas Bernard, Scott Notch
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Publication number: 20240235731Abstract: Systems and techniques for forward error correction decode processing power reduction are described herein. A first codeword is identified in a network transmission. A conditional decoding window is generated that begins with the first codeword. The conditional decoding window is aligned with a frame of the network transmission. A report is generated that includes an indication of relevance of the conditional decoding window to a network device. The conditional decoding window and the report are transmitted to the network device. A conditional decoding window is received that includes a first codeword. The first codeword is decoded to determine a second codeword. A report is obtained that includes a codeword relevance bit for the second codeword. Upon a determination that the codeword relevance bit indicates that the second codeword is irrelevant, the second codeword is discarded without decoding the second codeword.Type: ApplicationFiled: January 11, 2023Publication date: July 11, 2024Inventors: Christopher Thomas Bernard, Scott Notch