Abstract: An aperiodic mapping procedure for the mapping of logical to physical addresses is defined as a permutation function for generating optimized stride accesses in an interleaved multiple device system such as a large, parallel processing shared memory system wherein the function comprises a bit-matrix multiplication of a presented first (logical) address with a predetermined matrix to produce a second (physical) address. The permutation function maps the address from a first to a second address space for improved memory performance in such an interleaved memory system. Assuming that the memory has n logical address bits and 2.sub.d separately accessible memory devices (where d.ltoreq.n) and a second address that utilizes n-d bits of the first address as the offset within the referenced device node. The procedure includes performing a bit matrix multiplication between successive roows of the said matrix and bits of the first address to produce successive d bits of the second address.