Abstract: Certain aspects of the present disclosure provide for wireless sensor packages to monitor various oilfield equipment health status, such as bearing wear and detect out-of-balance condition on reciprocating rod lifts (RRLs). Equipment health data can be collected, analyzed and stored by an IoT gateway, which is a small form-factor, ruggedized, low-power Intel processor computer running a novel message-oriented middleware software stack that leverages the MQTT protocol. Data may subsequently be transmitted to a cloud service via the internet via to a datacenter through SCADA, for analysis and action.

Abstract: The present disclosure describes implementation of wireless sensor packages to monitor various oilfield equipment health status, such as bearing wear and detect out-of-balance condition on reciprocating rod lifts (RRLs). Equipment health data can be collected, analyzed and stored by an IoT gateway, which is a small form-factor, ruggedized, low-power Intel processor computer running a novel message-oriented middleware software stack that leverages the MQTT protocol. Data may subsequently be transmitted to a cloud service via the internet via to a datacenter through SCADA, for analysis and action.

Abstract: Methods and systems of process control and yield management for semiconductor device manufacturing based on predictions of final device performance are presented herein. Estimated device performance metric values are calculated based on one or more device performance models that link parameter values capable of measurement during process to final device performance metrics. In some examples, an estimated value of a device performance metric is based on at least one structural characteristic and at least one band structure characteristic of an unfinished, multi-layer wafer. In some examples, a prediction of whether a device under process will fail a final device performance test is based on the difference between an estimated value of a final device performance metric and a specified value. In some examples, an adjustment in one or more subsequent process steps is determined based at least in part on the difference.

Abstract: The subject technology discloses configurations for receiving, by a first process, a set of input events from an application in which the set of input events includes a set of input update commands. The first process writes the set of input update commands into a low-latency graphics pipeline. The subject technology dispatches, by the first process, the set of input update commands from the low-latency graphics pipeline to a second process. The second process receives the set of input update commands from the low-latency graphics pipeline. The subject technology then writes, by the second process, a set of input data into a shared graphics processing unit (GPU) texture.

Abstract: A VCSEL with undoped top mirror. The VCSEL is formed from an epitaxial structure deposited on a substrate, and a periodically doped conduction layer is coupled to the undoped top minor. A periodically doped spacer layer is coupled to an active region. An undoped bottom minor coupled to the periodically doped spacer layer. A first intracavity contact is coupled to the periodically doped conduction layer and a second intracavity contact is coupled to the periodically doped spacer layer.

Abstract: Processing an input event within an application includes detecting an input event within an application executing on a first thread, the input event being associated with an event handler. A separate execution corresponding to a current state of the application is performed on a second thread based on the event handler associated with the input event. Within the separate execution, a determination is made whether the event handler modifies at least one of a document associated with the application or a default behavior of the application. In a case where the event handler does not modify at least one of the document or the behavior, the subject technology refrains from invoking the event handler on the first thread.

Abstract: Methods and systems of process control and yield management for semiconductor device manufacturing based on predictions of final device performance are presented herein. Estimated device performance metric values are calculated based on one or more device performance models that link parameter values capable of measurement during process to final device performance metrics. In some examples, an estimated value of a device performance metric is based on at least one structural characteristic and at least one band structure characteristic of an unfinished, multi-layer wafer. In some examples, a prediction of whether a device under process will fail a final device performance test is based on the difference between an estimated value of a final device performance metric and a specified value. In some examples, an adjustment in one or more subsequent process steps is determined based at least in part on the difference.

Abstract: A VCSEL with undoped top mirror. The VCSEL is formed from an epitaxial structure deposited on a substrate, and a periodically doped conduction layer is coupled to the undoped top minor. A periodically doped spacer layer is coupled to an active region. An undoped bottom minor coupled to the periodically doped spacer layer. A first intracavity contact is coupled to the periodically doped conduction layer and a second intracavity contact is coupled to the periodically doped spacer layer.

Abstract: A VCSEL with undoped mirrors. An essentially undoped bottom DBR mirror is formed on a substrate. A periodically doped first conduction layer region is formed on the bottom DBR mirror. The first conduction layer region is heavily doped at a location where the optical electric field is at about a minimum. An active layer, including quantum wells, is on the first conduction layer region. A periodically doped second conduction layer region is connected to the active layer. The second conduction layer region is heavily doped where the optical electric field is at a minimum. An aperture is formed in the epitaxial structure above the quantum wells. A top mirror coupled to the periodically doped second conduction layer region. The top mirror is essentially undoped and formed in a mesa structure. An oxide is formed around the mesa structure to protect the top mirror during wet oxidation processes.

Abstract: A VCSEL with undoped top mirror. The VCSEL is formed from an epitaxial structure deposited on a substrate. A doped bottom mirror is formed on the substrate. An active layer that includes quantum wells is formed on the bottom mirror. A periodically doped conduction layer is formed on the active layer. The periodically doped conduction layer is heavily doped at locations where the optical energy is at a minimum when the VCSEL is in operation. A current aperture is used between the conduction layer and the active region. An undoped top mirror is formed on the heavily doped conduction layer.

Abstract: A VCSEL with undoped top mirror. The VCSEL is formed from an epitaxial structure deposited on a substrate. A doped bottom mirror is formed on the substrate. An active layer that includes quantum wells is formed on the bottom mirror. A periodically doped conduction layer is formed on the active layer. The periodically doped conduction layer is heavily doped at locations where the optical energy is at a minimum when the VCSEL is in operation. A current aperture is used between the conduction layer and the active region. An undoped top mirror is formed on the heavily doped conduction layer.

Abstract: A VCSEL with undoped mirrors. An essentially undoped bottom DBR mirror is formed on a substrate. A periodically doped first conduction layer region is formed on the bottom DBR mirror. The first conduction layer region is heavily doped at a location where the optical electric field is at about a minimum. An active layer, including quantum wells, is on the first conduction layer region. A periodically doped second conduction layer region is connected to the active layer. The second conduction layer region is heavily doped where the optical electric field is at a minimum. An aperture is formed in the epitaxial structure above the quantum wells. A top mirror coupled to the periodically doped second conduction layer region. The top mirror is essentially undoped and formed in a mesa structure. An oxide is formed around the mesa structure to protect the top mirror during wet oxidation processes.

Abstract: A VCSEL with undoped top mirror. The VCSEL is formed from an epitaxial structure deposited on a substrate. A doped bottom mirror is formed on the substrate. An active layer that includes quantum wells is formed on the bottom mirror. A periodically doped conduction layer is formed on the active layer. The periodically doped conduction layer is heavily doped at locations where the optical energy is at a minimum when the VCSEL is in operation. A current aperture is used between the conduction layer and the active region. An undoped top mirror is formed on the heavily doped conduction layer.

Abstract: A VCSEL with undoped mirrors. An essentially undoped bottom DBR mirror is formed on a substrate. A periodically doped first conduction layer region is formed on the bottom DBR mirror. The first conduction layer region is heavily doped at a location where the optical electric field is at about a minimum. An active layer, including quantum wells, is on the first conduction layer region. A periodically doped second conduction layer region is connected to the active layer. The second conduction layer region is heavily doped where the optical electric field is at a minimum. An aperture is formed in the epitaxial structure above the quantum wells. A top mirror coupled to the periodically doped second conduction layer region. The top mirror is essentially undoped and formed in a mesa structure. An oxide is formed around the mesa structure to protect the top mirror during wet oxidation processes.

Abstract: A VCSEL with nearly planar intracavity contact. A bottom DBR mirror is formed on a substrate. A first conduction layer region is formed on the bottom DBR mirror. An active layer, including quantum wells, is on the first conduction layer region. A trench is formed into the active layer region. The trench is formed in a wagon wheel configuration with spokes providing mechanical support for the active layer region. The trench is etched approximately to the first conduction layer region. Proton implants are provided in the wagon wheel and configured to render the spokes of the wagon wheel insulating. A nearly planar electrical contact is formed as an intracavity contact for connecting the bottom of the active region to a power supply. The nearly planar electrical contact is formed in and about the trench.