Patents by Inventor Scott Pitkethly
Scott Pitkethly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9911470Abstract: A memory circuit that presents input data at a data output promptly on receiving a clock pulse includes upstream and downstream memory logic and selection logic. The upstream memory logic is configured to latch the input data on receiving the clock pulse. The downstream memory logic is configured to store the latched input data. The selection logic is configured to expose a logic level dependent on whether the upstream memory logic has latched the input data, the exposed logic level derived from the input data before the input data is latched, and from the latched input data after the input data is latched.Type: GrantFiled: April 13, 2012Date of Patent: March 6, 2018Assignee: NVIDIA CORPORATIONInventors: Venkata Kottapalli, Scott Pitkethly, Christian Klingner, Matthew Gerlach
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Patent number: 9595968Abstract: A cross point switch, in accordance with one embodiment, includes a plurality of tri-state repeaters coupled to form a plurality of multiplexers. Each set of corresponding tri-state repeaters in the plurality of multiplexers share a front end module such that delay through the cross point switch due to input capacitance is reduced as compared to conventional cross point switches.Type: GrantFiled: October 13, 2015Date of Patent: March 14, 2017Assignee: INTELLECTUAL VENTURES HOLDING 81 LLCInventors: Robert P. Masleid, Scott Pitkethly
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Patent number: 9569214Abstract: In one embodiment, in an execution pipeline having a plurality of execution subunits, a method of using a bypass network to directly forward data from a producing execution subunit to a consuming execution subunit is provided. The method includes producing output data with the producing execution subunit, consuming input data with the consuming execution subunit, for one or more intervening operations whose input is the output data from the producing execution subunit and whose output is the input data to the consuming execution subunit, evaluating those one or more intervening operations to determine whether their execution would compose an identify function, and if the one or more intervening operations would compose such an identity function, controlling the bypass network to forward the producing execution subunit's output data directly to the consuming execution subunit.Type: GrantFiled: December 27, 2012Date of Patent: February 14, 2017Assignee: NVIDIA CORPORATIONInventors: Gokul Govindu, Parag Gupta, Scott Pitkethly, Guillermo J. Rozas
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Publication number: 20160036446Abstract: A cross point switch, in accordance with one embodiment, includes a plurality of tri-state repeaters coupled to form a plurality of multiplexers. Each set of corresponding tri-state repeaters in the plurality of multiplexers share a front end module such that delay through the cross point switch due to input capacitance is reduced as compared to conventional cross point switches.Type: ApplicationFiled: October 13, 2015Publication date: February 4, 2016Inventors: Robert P. Masleid, Scott Pitkethly
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Patent number: 9178505Abstract: A cross point switch, in accordance with one embodiment of the present invention, includes a plurality of tri-state repeaters coupled to form a plurality of multiplexers. Each set of corresponding tri-state repeaters in the plurality of multiplexers share a front end module such that delay through the cross point switch due to input capacitance is reduced as compared to conventional cross point switches.Type: GrantFiled: March 1, 2010Date of Patent: November 3, 2015Assignee: INTELLECTUAL VENTURE FUNDING LLCInventors: Robert P. Masleid, Scott Pitkethly
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Patent number: 8848458Abstract: A memory circuit in which a level of a first data input appears promptly at an output in response to a clock pulse received. The circuit includes a flip-flop triggered by the clock pulse and configured to receive the first data input and drive a second data input. The circuit also includes a first control input driven by the clock pulse, a second control input driven by the flip-flop and selection logic configured to receive the first and second data inputs and the first and second control inputs. The selection logic is configured to drive the output of the memory circuit to the level of the first data input or of the second data input depending on the first and second control inputs.Type: GrantFiled: December 15, 2011Date of Patent: September 30, 2014Assignee: Nvidia CorporationInventors: Venkata Kottapalli, Scott Pitkethly, Christian Klingner, Matthew Gerlach
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Patent number: 8838665Abstract: In one embodiment, a microprocessor includes fetch logic for retrieving an instruction, decode logic configured to identify a plurality of operands and a multiply operation specified in the instruction, and execution logic configured to receive the plurality of operands and the multiply operation. The execution logic includes a first logic path configured to perform the multiply operation on the plurality of operands and output a result, and a second logic path, arranged in parallel with the first logic path, configured to output metadata associated with the result of the multiply operation.Type: GrantFiled: November 14, 2011Date of Patent: September 16, 2014Assignee: Nvidia CorporationInventor: Scott Pitkethly
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Publication number: 20140189316Abstract: In one embodiment, in an execution pipeline having a plurality of execution subunits, a method of using a bypass network to directly forward data from a producing execution subunit to a consuming execution subunit is provided. The method includes producing output data with the producing execution subunit, consuming input data with the consuming execution subunit, for one or more intervening operations whose input is the output data from the producing execution subunit and whose output is the input data to the consuming execution subunit, evaluating those one or more intervening operations to determine whether their execution would compose an identify function, and if the one or more intervening operations would compose such an identity function, controlling the bypass network to forward the producing execution subunit's output data directly to the consuming execution subunit.Type: ApplicationFiled: December 27, 2012Publication date: July 3, 2014Applicant: NVIDIA CORPORATIONInventors: Gokul Govindu, Parag Gupta, Scott Pitkethly, Guillermo J. Rozas
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Patent number: 8762444Abstract: In one embodiment, a microprocessor includes fetch logic for retrieving an instruction, decode logic configured to identify an arithmetic operation specified in the instruction, and execution logic configured to receive operands specified by the instruction. The execution logic includes a primary logic path configured to perform the arithmetic operation on such operands and a secondary parallel logic path configured to output metadata associated with the result of the arithmetic operation.Type: GrantFiled: September 28, 2011Date of Patent: June 24, 2014Assignee: NVIDIA CorporationInventors: Peter Gentle, Scott Pitkethly
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Publication number: 20130155781Abstract: A memory circuit in which a level of a first data input appears promptly at an output in response to a clock pulse received. The circuit includes a flip-flop triggered by the clock pulse and configured to receive the first data input and drive a second data input. The circuit also includes a first control input driven by the clock pulse, a second control input driven by the flip-flop and selection logic configured to receive the first and second data inputs and the first and second control inputs. The selection logic is configured to drive the output of the memory circuit to the level of the first data input or of the second data input depending on the first and second control inputs.Type: ApplicationFiled: December 15, 2011Publication date: June 20, 2013Applicant: NVIDIA CORPORATIONInventors: Venkata Kottapalli, Scott Pitkethly, Christian Klingner, Matthew Gerlach
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Publication number: 20130155783Abstract: A memory circuit that presents input data at a data output promptly on receiving a clock pulse includes upstream and downstream memory logic and selection logic. The upstream memory logic is configured to latch the input data on receiving the clock pulse. The downstream memory logic is configured to store the latched input data. The selection logic is configured to expose a logic level dependent on whether the upstream memory logic has latched the input data, the exposed logic level derived from the input data before the input data is latched, and from the latched input data after the input data is latched.Type: ApplicationFiled: April 13, 2012Publication date: June 20, 2013Applicant: NVIDIA CORPORATIONInventors: Venkata Kottapalli, Scott Pitkethly, Christian Klingner, Matthew Gerlach
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Patent number: 8451025Abstract: An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal. The advanced repeater may further include circuitry for producing a delayed version of the signal.Type: GrantFiled: September 19, 2011Date of Patent: May 28, 2013Inventor: Scott Pitkethly
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Publication number: 20130080491Abstract: In one embodiment, a microprocessor includes fetch logic for retrieving an instruction, decode logic configured to identify a plurality of operands and a multiply operation specified in the instruction, and execution logic configured to receive the plurality of operands and the multiply operation. The execution logic includes a first logic path configured to perform the multiply operation on the plurality of operands and output a result, and a second logic path, arranged in parallel with the first logic path, configured to output metadata associated with the result of the multiply operation.Type: ApplicationFiled: November 14, 2011Publication date: March 28, 2013Applicant: NIVIDIA CORPORATIONInventor: Scott Pitkethly
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Publication number: 20130080740Abstract: In one embodiment, a microprocessor includes fetch logic for retrieving an instruction, decode logic configured to identify an arithmetic operation specified in the instruction, and execution logic configured to receive operands specified by the instruction. The execution logic includes a primary logic path configured to perform the arithmetic operation on such operands and a secondary parallel logic path configured to output metadata associated with the result of the arithmetic operation.Type: ApplicationFiled: September 28, 2011Publication date: March 28, 2013Applicant: NVIDIA CORPORATIONInventors: Peter Gentle, Scott Pitkethly
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Publication number: 20120242387Abstract: An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal. The advanced repeater may further include circuitry for producing a delayed version of the signal.Type: ApplicationFiled: September 19, 2011Publication date: September 27, 2012Inventor: Scott Pitkethly
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Patent number: 8022731Abstract: An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal. The advanced repeater may further include circuitry for producing a delayed version of the signal.Type: GrantFiled: April 14, 2010Date of Patent: September 20, 2011Inventor: Scott Pitkethly
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Patent number: 7872492Abstract: A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down node. The primary latch records state of the triple latch flip-flop system. The output for outputting a logic value based upon outputs of the pull up latch, pull down latch and the primary latch.Type: GrantFiled: February 24, 2009Date of Patent: January 18, 2011Inventors: Scott Pitkethly, Robert P. Masleid
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Publication number: 20100295577Abstract: An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal. The advanced repeater may further include circuitry for producing a delayed version of the signal.Type: ApplicationFiled: April 14, 2010Publication date: November 25, 2010Inventor: Scott Pitkethly
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Patent number: 7768295Abstract: An advanced repeater utilizing signal distribution delay. In accordance with a first embodiment of the present invention, such an advanced repeater circuit comprises an output stage for driving an output signal line responsive to an input signal and a feedback loop coupled to said output signal line for changing state of said output stage subsequent to a delay after a transition of said output signal. The delay is due to transmission line effects of said output signal line.Type: GrantFiled: May 20, 2008Date of Patent: August 3, 2010Inventors: Scott Pitkethly, Robert Paul Masleid
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Publication number: 20100156504Abstract: A cross point switch, in accordance with one embodiment of the present invention, includes a plurality of tri-state repeaters coupled to form a plurality of multiplexers. Each set of corresponding tri-state repeaters in the plurality of multiplexers share a front end module such that delay through the cross point switch due to input capacitance is reduced as compared to conventional cross point switches.Type: ApplicationFiled: March 1, 2010Publication date: June 24, 2010Inventors: Robert P. Masleid, Scott Pitkethly