Abstract: Bond pad structures and methods for fabricating bond pad structures. A bond pad and a plurality of fill lines are formed on the top surface of a dielectric layer. The fill lines are arranged on the top surface of the dielectric layer adjacent to the bond pad, and may be separated from the bond pad by a fill keep-out zone. One or more Under Bump Metallurgy (UBM) layers may be arranged on the bond pad and may extend outwardly to overlap with the fill lines.

Abstract: Bond pad structures and methods for fabricating bond pad structures. A bond pad and a plurality of fill lines are formed on the top surface of a dielectric layer. The fill lines are arranged on the top surface of the dielectric layer adjacent to the bond pad, and may be separated from the bond pad by a fill keep-out zone. One or more Under Bump Metallurgy (UBM) layers may be arranged on the bond pad and may extend outwardly to overlap with the fill lines.

Abstract: A fuse (43) is formed overlying a passivation layer (35) and under a packaging material (55, 70). In one embodiment, a fuse (43) is blown before the packaging material (55, 70) is formed. In some embodiments, the fuse (43) may be formed of metal (47), a metal nitride (42) or a combination thereof.

Abstract: A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material. The selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad.

Abstract: Utilizing magnetic features located on different structures having semiconductor devices to align the structures when contacting the structures together. The magnetic features on each structure are of opposite polarity and provide magnetic forces for alignment of the structures. The magnetic forces can also be used to sense position and move the structures into an aligned position. In some examples, the structures include die with semiconductor devices. In one example, the structures are wafers with multiple die. In other examples, one of the structures is a die and the other is a wafer.

Abstract: A reciprocal design symmetry allows stacked wafers or die on wafer to use identical designs or designs that vary only by a few layers (e.g. metal interconnect layers). Flipping or rotating one die or wafer allows the stacked die to have a reciprocal orientation with respect to each other which may be used to decrease the interconnect required between the vertically stacked die and or wafers. Flipping and/or rotating may also be used to improve heat dissipation when wafer and/or die are stacked. The stacked wafers or die may then be packaged.

Abstract: A method of assembling an electronic device includes testing a first wafer of first die to identify the location of functional first die and dividing the first wafer into a set of panels, wherein a panel includes an M×N array of first die. A panel is bonded to a panel site of a second wafer to form a panel stack wherein a panel site defines an M×N array of second die in the second wafer. The panel stack is sawed into a devices comprising a first die bonded to a second die. Dividing the first wafer into panels may be done according statically or dynamically (to maximize the number of panels having a yield exceeding a specified threshold). Binning of the panels and panel sites according to functional die patterns may be performed to preferentially bond panels to panel sites of the same bin.

Abstract: A bump shear test is disclosed for evaluating the mechanical integrity of low-k interconnect stacks in an integrated circuit which includes a die test structure (11) having a stiff structural component (501, 502) positioned above and affixed to a conductive metal pad (103) formed in a last metal layer (104). The die test structure (11) may also include a dedicated support structure (41) below the conductive metal pad which includes a predetermined pattern of metal lines formed in the interconnect layers (18, 22, 26). After mounting the integrated circuit in a test device, a shear knife (601) is positioned for lateral movement to cause the shear knife to contact the stiff structural component (501). Any damage to the die test structure caused by the lateral movement of the shear knife may be assessed to evaluate the mechanical integrity of the interconnect stack.

Abstract: A technique for alleviating the problems of defects caused by stress applied to bond pads (32) includes, prior to actually making an integrated circuit (10), adding dummy metal lines (74, 76) to interconnect layers (18, 22, 26) to increase the metal density of the interconnect layers. These problems are more likely when the interlayer dielectrics (16, 20, 24) between the interconnect layers are of a low-k material. A critical area or force area (64) around and under each bond pad defines an area in which a defect may occur due to a contact made to that bond pad. Any interconnect layer in such a critical area that has a metal density below a certain percentage can be the cause of a defect in the interconnect layers. Any interconnect layer that has a metal density below that percentage in the critical area has dummy metal lines added to it.

Abstract: A semiconductor device is attached to a heat sink by glue that is both thermally conductive and magnetically permeable. The glue fills different features in the surface of the semiconductor device so that there is good coupling between the semiconductor device and the heat sink. The glue is filled with magnetic particles so that the glue is magnetically permeable. The semiconductor device is formed with the heat sink at the wafer level and then singulated after attachment of the heat sink with the glue.

Abstract: A back side body contact for a transistor that extends through an opening in an insulating layer located adjacent to the backside of the body. The backside contact is coupled to an interconnect on the backside. In some examples, the interconnect is coupled to an interconnect located with respect the other side of an active layer which is coupled to a body voltage bias source.

Abstract: An integrated circuit with a first plurality of transistors formed on a first wafer and second plurality of transistors formed on a second wafer. At least a substantial majority of the transistor of the first transistor are of a first conductivity type and at least a substantial majority of the transistors of the second plurality are of a second conductivity type. After wafers are bonded together, a portion of the second wafer is removed wherein the strain of the channels of the second plurality of transistors is more compressive than the strain of the channels of the first plurality of transistors.

Abstract: A semiconductor device is attached to a heat sink by glue that is both thermally conductive and magnetically permeable. The glue fills different features in the surface of the semiconductor device so that there is good coupling between the semiconductor device and the heat sink. The glue is filled with magnetic particles so that the glue is magnetically permeable. The semiconductor device is formed with the heat sink at the wafer level and then singulated after attachment of the heat sink with the glue.

Abstract: A composite bond pad that is resistant to external forces that may be applied during probing or packaging operations is presented. The composite bond pad includes a non-self-passivating conductive bond pad (134) that is formed over a semiconductor substrate (100). A dielectric layer (136) is then formed over the conductive bond pad (134). Portions of the dielectric layer (136) are removed such that the dielectric layer (136) becomes perforated and a portion of the conductive bond pad (134) is exposed. Remaining portions of the dielectric layer (136) form support structures (138) that overlie that bond pad. A self-passivating conductive capping layer (204) is then formed overlying the bond pad structure, where the perforations in the dielectric layer (136) allow for electrical contact between the capping layer (204) and the exposed portions of the underlying bond pad (134).