Abstract: A multifunctional signal path of the present disclosure is able to distinguish between normal blink patterns and unique purposeful blinking patterns in order to control functionality in a powered ophthalmic lens. The multifunctional signal path of the present disclosure is able to detect the presence or absence of a non-human-capable communication sequence, such as a computer-generated communication signal of alternating light patterns that are unlikely to be accomplished by a human eye. The multifunctional signal path of the present disclosure is also able to be integrated into an ophthalmic device.

Abstract: This invention discloses methods of manufacture and use of an energized Ophthalmic Device with an incorporated Storage Mode for a power source, the method of manufacturing said device, and a method of activation that may restore the power source to an operational mode.

Abstract: This invention discloses an energized Ophthalmic Device with incorporated low energy consuming modes. In some embodiments, media inserts with incorporated low energy consuming modes are described.

Abstract: A resistorless amplifier circuit uses integrated operational transconductance amplifiers to realize a plurality of circuit transfer functions. The preferred embodiment produces an output signal voltage V.sub.out (500) that is either g.sub.m1 /g.sub.m3 or g.sub.m1 /(g.sub.m3 -g.sub.m1) times the input signal voltage V.sub.in (400). Additionally, an alternative embodiment implements a resistorless summing and subtracting operational transconductance amplifier circuit that realizes an output signal voltage as follows: ##EQU1## The resistorless amplifier circuit includes a first operational transconductance amplifier (100) with a transconductance g.sub.m1, a second operational transconductance amplifier (200) with a transconductance g.sub.m2, and a third operational transconductance amplifier (300) with a transconductance g.sub.m3.

Abstract: A PLL circuit (401), including a VCO (420) having a trimming port (418) and a tuning port (416), a PLL controller (404), a variable voltage source (408), a voltage measuring circuit (426) and a multiplexer (412, 414, 428), performs automatic trimming of the VCO (420). The PLL circuit (401) accomplishes this by initiating a trimming mode that controls the multiplexer so that it couples the output of the PLL controller (404) to the trimming port (418), and the output of the variable voltage source (408) to the tuning port (416), thereby to phase lock the VCO (420) to the reference frequency signal (421). The PLL circuit (401) then measures, by way of the voltage measuring circuit (426), a voltage at the trimming port (418), switches the PLL circuit (401) to an operational mode, and then adjusts the variable voltage source (408) to be substantially equal to the voltage measured.

Abstract: A communication receiver (100) employs a discrete time digital phase locked loop (142) for maintaining a generated signal (144) locked to a reference signal (136). The discrete time digital phase locked loop (142) includes a phase detector (202), an accumulator (219), an adder (227), and a controlled oscillator (232). The accumulator (219) is connected to the phase detector (202) and a reference signal (136) for calculating an accumulator output value equal to a first sum of a current sample generated by the phase detector (202), and all of the plurality of discrete phase error samples produced prior to the current sample. The adder (227) is connected to the phase detector (202) and the accumulator (219) for forming a second sum of the current sample and the accumulator output value. The controlled oscillator (232) receives the second sum, which is utilized for controlling the controlled oscillator (232).

Abstract: A voltage controlled tunable resonant circuit (100) has at least two resonant frequency ranges and reduced self modulation, and includes a resonant element (120), a variable reactance element (130), and a first voltage variable capacitor (VVC) (150). The variable reactance element (130) is coupled to the resonant element (120). The VVC (150) has two fixed capacitance values corresponding to two fixed capacitance bias voltage ranges, and is coupled to the resonant element (120) and the variable reactance element (130). The first VVC (150) is controlled by a first DC bias voltage (190) selected to be within one of the two fixed capacitance bias voltage ranges to establish one of the two resonant frequency ranges over which the voltage controlled tunable resonant circuit (100) is tuned by variation of the variable reactance element (130).