Patents by Inventor Scott R. Summerfelt

Scott R. Summerfelt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9991120
    Abstract: A process for forming an integrated circuit with a dilution doped resistor with a resistance that may be tuned by partially blocking the implant used to dope the resistor. A process for forming an integrated circuit with a dilution doped polysilicon resistor by partially blocking the resistor dopant implant from a portion of the polysilicon resistor body.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: June 5, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Scott K. Montgomery, Scott R. Summerfelt
  • Patent number: 9773793
    Abstract: A transistor structure with stress enhancement geometry aligned above the channel region. Also, a transistor structure with stress enhancement geometries located above and aligned with opposite sides of the channel region. Furthermore, methods for fabricating integrated circuits containing transistors with stress enhancement geometries.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: September 26, 2017
    Assignee: TEXAS INSTUMENTS INCORPORATED
    Inventors: Scott R. Summerfelt, Rajni J. Aggarwal, Shaoping Tang
  • Patent number: 9619606
    Abstract: A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is determined (212). A pattern of the dummy fill layer is selected to produce a predetermined density (216). The selected pattern is placed in the sub-region (208).
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: April 11, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Scott R. Summerfelt, Robert G. Fleck
  • Patent number: 9536822
    Abstract: An integrated circuit containing hydrogen permeable dummy vias configured in a linear or rectangular array and symmetrically positioned over a component in the integrated circuit. An integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components. A process of forming an integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: January 3, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Scott R. Summerfelt, Rajni J. Aggarwal
  • Patent number: 9218981
    Abstract: An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: December 22, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gul B. Basim, Scott R. Summerfelt, Ted S. Moise
  • Publication number: 20150187583
    Abstract: A process for forming an integrated circuit with a dilution doped resistor with a resistance that may be tuned by partially blocking the implant used to dope the resistor. A process for forming an integrated circuit with a dilution doped polysilicon resistor by partially blocking the resistor dopant implant from a portion of the polysilicon resistor body.
    Type: Application
    Filed: December 19, 2014
    Publication date: July 2, 2015
    Inventors: Scott K. Montgomery, Scott R. Summerfelt
  • Patent number: 9048297
    Abstract: An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure. An upper conductive structure contacts a top surface of the vertical interconnect. A process of forming an integrated circuit that includes forming a vertical interconnect that has a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure, and an upper conductive structure contacts a top surface of the vertical interconnect.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: June 2, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Scott R. Summerfelt
  • Publication number: 20140370621
    Abstract: An integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. A method for forming an integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer.
    Type: Application
    Filed: August 28, 2014
    Publication date: December 18, 2014
    Inventors: Rajni J. Aggarwal, Scott R. Summerfelt, Gul B. Basim, Ted S. Moise
  • Patent number: 8907446
    Abstract: An integrated circuit structure with a metal-to-metal capacitor and a metallic device such as a resistor, effuse, or local interconnect where the bottom plate of the capacitor and the metallic device are formed with the same material layers. A process for forming a metallic device along with a metal-to-metal capacitor with no additional manufacturing steps.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: December 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Scott R. Summerfelt, Byron L. Williams, Scott K. Montgomery, James Klawinsky, Asad M. Haider
  • Patent number: 8883629
    Abstract: A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is determined (212). A pattern of the dummy fill layer is selected to produce a predetermined density (216). The selected pattern is placed in the sub-region (208).
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: November 11, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Scott R. Summerfelt, Robert G. Fleck
  • Publication number: 20140308762
    Abstract: A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is determined (212). A pattern of the dummy fill layer is selected to produce a predetermined density (216). The selected pattern is placed in the subregion (208).
    Type: Application
    Filed: June 26, 2014
    Publication date: October 16, 2014
    Inventors: Scott R. Summerfelt, Robert G. Fleck
  • Publication number: 20140215425
    Abstract: A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is determined (212). A pattern of the dummy fill layer is selected to produce a predetermined density (216). The selected pattern is placed in the sub-region (208).
    Type: Application
    Filed: March 31, 2014
    Publication date: July 31, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Scott R. Summerfelt, Robert G. Fleck
  • Patent number: 8779485
    Abstract: An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: July 15, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Kezhakkedath R. Udayakumar, Scott R. Summerfelt, Ted S. Moise, Manoj K. Jain
  • Patent number: 8778700
    Abstract: An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: July 15, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Kezhakkedath R. Udayakumar, Scott R. Summerfelt, Ted S. Moise, Manoj K. Jain
  • Publication number: 20140094028
    Abstract: An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure. An upper conductive structure contacts a top surface of the vertical interconnect. A process of forming an integrated circuit that includes forming a vertical interconnect that has a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure, and an upper conductive structure contacts a top surface of the vertical interconnect.
    Type: Application
    Filed: December 5, 2013
    Publication date: April 3, 2014
    Inventor: Scott R. Summerfelt
  • Patent number: 8669644
    Abstract: An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: March 11, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Gul B. Basim, Scott R. Summerfelt, Ted S. Moise
  • Patent number: 8659165
    Abstract: An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure. An upper conductive structure contacts a top surface of the vertical interconnect. A process of forming an integrated circuit that includes forming a vertical interconnect that has a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure, and an upper conductive structure contacts a top surface of the vertical interconnect.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: February 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Scott R. Summerfelt
  • Patent number: 8658474
    Abstract: An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure. An upper conductive structure contacts a top surface of the vertical interconnect. A process of forming an integrated circuit that includes forming a vertical interconnect that has a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure, and an upper conductive structure contacts a top surface of the vertical interconnect.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: February 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Scott R. Summerfelt
  • Publication number: 20140051234
    Abstract: An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.
    Type: Application
    Filed: October 29, 2013
    Publication date: February 20, 2014
    Inventors: Gul B. Basim, Scott R. Summerfelt, Ted S. Moise
  • Patent number: 8586130
    Abstract: An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in the reflective layer, enabling registration of the alignment mark using common photolithographic scanners and steppers. The reflective layer may be one or more layers, and may be metallic, dielectric or both. The reflective layer may be global over the entire IC or may be local to the alignment mark area. The reflective layer may be removed during subsequent processing, possibly with assist from an added etch stop layer, or may remain in the completed IC. The disclosed alignment mark structure is applicable to an IC with a stack of ferroelectric capacitor materials.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: November 19, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Stephen Arion Meisner, Scott R. Summerfelt