Patents by Inventor Scott Robins

Scott Robins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10894977
    Abstract: Compositions and methods are described for standardizing the DNA amplification efficiencies of a highly heterogeneous set of oligonucleotide primers as may typically be used to amplify a heterogeneous set of DNA templates that contains rearranged lymphoid cell DNA encoding T cell receptors (TCR) or immunoglobulins (IG). The presently disclosed embodiments are useful to overcome undesirable bias in the utilization of a subset of amplification primers, which leads to imprecision in multiplexed high throughput sequencing of amplification products to quantify unique TCR or Ig encoding genomes in a sample. Provided is a template composition comprising a diverse plurality of template oligonucleotides in substantially equimolar amounts, for use as a calibration standard for amplification primer sets. Also provided are methods for identifying and correcting biased primer efficiency during amplification.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: January 19, 2021
    Assignee: Adaptive Biotechnologies corporation
    Inventors: Harlan Saul Robins, Christopher Scott Carlson, Robert J. Livingston, Ryan O. Emerson, Anna M. Sherwood
  • Publication number: 20200024717
    Abstract: A steel strip that has a coating of an Al—Zn—Si alloy that contains 0.3-10 wt. % Mg and 0.005-0.2 wt. % V.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: Ross McDowall Smith, Qiyang Liu, Joe Williams, Aaron Kiffer Neufeld, Scott Robin Griffiths
  • Publication number: 20190203281
    Abstract: Compositions and methods are described for standardizing the DNA amplification efficiencies of a highly heterogeneous set of oligonucleotide primers as may typically be used to amplify a heterogeneous set of DNA templates that contains rearranged lymphoid cell DNA encoding T cell receptors (TCR) or immunoglobulins (IG). The presently disclosed embodiments are useful to overcome undesirable bias in the utilization of a subset of amplification primers, which leads to imprecision in multiplexed high throughput sequencing of amplification products to quantify unique TCR or Ig encoding genomes in a sample. Provided is a template composition comprising a diverse plurality of template oligonucleotides in substantially equimolar amounts, for use as a calibration standard for amplification primer sets. Also provided are methods for identifying and correcting biased primer efficiency during amplification.
    Type: Application
    Filed: January 8, 2019
    Publication date: July 4, 2019
    Inventors: Harlan Saul ROBINS, Christopher Scott CARLSON, Robert J. LIVINGSTON, Ryan O. EMERSON, Anna M. SHERWOOD
  • Publication number: 20130011693
    Abstract: A steel strip that has a coating of an Al—Zn—Si alloy that contains 0.3-10 wt. % Mg and 0.005-0.2 wt. % V.
    Type: Application
    Filed: January 6, 2011
    Publication date: January 10, 2013
    Applicant: BLUESCOPE STEEL LIMITED
    Inventors: Ross McDowall Smith, Qiyang Liu, Joe Williams, Aaron Kiffer Neufeld, Scott Robin Griffiths
  • Patent number: 8093107
    Abstract: A thyristor based semiconductor device includes a thyristor having cathode, P-base, N-base and anode regions disposed in electrical series relationship. The N-base region for the thyristor has a cross-section that defines an inverted “T” shape, wherein a buried well in semiconductor material forms is operable as a part of the N-base. The stem to the inverted “T” shape extends from the upper surface of the semiconductor material to the buried well. The P-base region for the thyristor extends laterally outward from a side of the stem that is opposite the anode region of the thyristor, and is further bounded between the buried well and a surface of the semiconductor material. A thinned portion for the N-base is defined between the cathode region of the thyristor and the buried well, and may include supplemental dopant of concentration greater than that for some other portion of the N-base.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: January 10, 2012
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Farid Nemati, Scott Robins, Kevin J. Yang
  • Patent number: 8017998
    Abstract: Gettering contaminants for formation of integrated circuits on a semiconductor-on-insulator structure is described. A semiconductor-on-insulator structure is configured to attract contaminants. Contaminant attractor regions are formed using ion implantation into a semiconductor layer of the semiconductor-on-insulator structure. The semiconductor layer is located above a buried insulator layer of the semiconductor-on-insulator structure. The contaminant attractor regions are spaced away from active regions. Tiles are located on an upper surface of the buried insulator layer. The contaminant attractor regions are formed adjacent to, in close proximity to, or in the tiles. At least one dielectric layer laterally adjacent to the tiles and is disposed on the upper surface of the buried insulator layer. The at least one dielectric layer at least inhibits lateral migration of contaminants to the active regions.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: September 13, 2011
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Srinivasa R. Banna, Scott Robins
  • Patent number: 7968381
    Abstract: A semiconductor device having a thyristor-based device and a pass device exhibits characteristics that may include, for example, resistance to short channel effects that occur when conventional MOSFET devices are scaled smaller in connection with advancing technology. According to an example embodiment of the present invention, the semiconductor device includes a pass device having a channel in a fin portion over a semiconductor substrate, and a thyristor device coupled to the pass device. The fin has a top portion and a side portion and extends over the semiconductor substrate. The pass device includes source/drain regions separated by the channel and a gate facing and capacitively coupled to the side portion of the fin that includes the channel. The thyristor device includes anode and cathode end portions, each end portion having base and emitter regions, where one of the emitter regions is coupled to one of the source/drain regions of the pass device.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: June 28, 2011
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Andrew Horch, Scott Robins
  • Patent number: 7894256
    Abstract: A new memory cell contains only a single thyristor without the need to include an access transistor. A memory array containing these memory cells can be fabricated on bulk silicon wafer. The memory cell contains a thyristor body and a gate. The thyristor body has two end region and two base regions, and it is disposed on top of a well. The memory cell is positioned between two isolation regions, and the isolation regions are extended below the well. A first end region is connected to one of a word line, a bit line and a third line. A second end region is connected to another of the word line, bit line, and third line. The gate is connected to the remaining of the word line, bit line and third line.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: February 22, 2011
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Farid Nemati, Scott Robins, Kevin J. Yang
  • Patent number: 7894255
    Abstract: A new memory cell contains only a single thyristor without the need to include an access transistor. A memory array containing these memory cells can be fabricated on bulk silicon wafer. Each memory cell is separated from other memory cells by shallow trench isolation regions. The memory cell comprises a thyristor body and a gate. The thyristor body has two end region and two base regions. The gate is positioned over and insulated from at least a portion of one base region and offset from another base region. A first end region is connected to one of a word line, a bit line and a third line. A second end region is connected to another of the word line, bit line, and third line. The gate is connected to the remaining of the word line, bit line and third line.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: February 22, 2011
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Farid Nemati, Scott Robins, Kevin J. Yang
  • Patent number: 7859011
    Abstract: A semiconductor device may comprise a partially-depleted SOI MOSFET having a floating body region disposed between a source and drain. The floating body region may be driven to receive injected carriers for adjusting its potential during operation of the MOSFET. In a particular case, the MOSFET may comprise another region of semiconductor material in contiguous relationship with a drain/source region of the MOSFET and on a side thereof opposite to the body region. This additional region may be formed with a conductivity of type opposite the drain/source, and may establish an effective bipolar device per the body, the drain/source and the additional region. The geometries and doping thereof may be designed to establish a transport gain of magnitude sufficient to assist the injection of carriers into the floating body region, yet small enough to guard against inter-latching with the MOSFET.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: December 28, 2010
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Zachary K. Lee, Farid Nemati, Scott Robins
  • Patent number: 7858449
    Abstract: In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: December 28, 2010
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Kevin J. Yang, Farid Nemati, Scott Robins, James D. Plummer, Hyun-Jin Cho
  • Patent number: 7554130
    Abstract: An integrated circuit having memory, including thyristor-based memory cells, is described, where each of the thyristor-based memory cells includes a thyristor-based storage element and an access transistor. Where the thyristor-based storage element includes an anode region and a cathode region, a pair of the thyristor-based memory cells are commonly coupled via a bitline associated with the access transistor or via a reference voltage line coupled to the anode region. Bitline or anode regions are separated from one another by an isolation region. In another configuration, a bitline region has a locally implant-damaged region to inhibit charge transfer between the pair. In yet another configuration, a storage node contact or contacts respectively can extend over or are coupled to a storage node line extending over an isolation region. In this latter configuration, a source/drain region and the cathode region are separated from one another by an isolation region.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: June 30, 2009
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Scott Robins, Kevin J. Yang, Rajesh N. Gupta
  • Publication number: 20090162979
    Abstract: In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.
    Type: Application
    Filed: February 9, 2009
    Publication date: June 25, 2009
    Inventors: Kevin J. Yang, Farid Nemati, Scott Robins, James D. Plummer, Hyun-Jin Cho
  • Publication number: 20090140288
    Abstract: A semiconductor device may comprise a partially-depleted SOI MOSFET having a floating body region disposed between a source and drain. The floating body region may be driven to receive injected carriers for adjusting its potential during operation of the MOSFET. In a particular case, the MOSFET may comprise another region of semiconductor material in contiguous relationship with a drain/source region of the MOSFET and on a side thereof opposite to the body region. This additional region may be formed with a conductivity of type opposite the drain/source, and may establish an effective bipolar device per the body, the drain/source and the additional region. The geometries and doping thereof may be designed to establish a transport gain of magnitude sufficient to assist the injection of carriers into the floating body region, yet small enough to guard against inter-latching with the MOSFET.
    Type: Application
    Filed: February 9, 2009
    Publication date: June 4, 2009
    Inventors: Zachary K. Lee, Farid Nemati, Scott Robins
  • Patent number: 7491586
    Abstract: A method of fabricating a thyristor-based memory may include forming different opposite conductivity-type regions in silicon for defining a thyristor and an access device in series relationship. An activation anneal may activate dopants previously implanted for the different regions. A damaging implant of germanium or xenon or argon may be directed into select regions of the silicon including at least one p-n junction region for the access device and the thyristor. A re-crystallization anneal may then be performed to re-crystallize at least some of the damaged lattice structure resulting from the damaging implant. The re-crystallization anneal may use a temperature less than that of the previous activation anneal.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: February 17, 2009
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Andrew E Horch, Hyun-Jin Cho, Farid Nemati, Scott Robins, Rajesh N. Gupta, Kevin J. Yang
  • Patent number: 7489008
    Abstract: A semiconductor device may comprise a partially-depleted SOI MOSFET having a floating body region disposed between a source and drain. The floating body region may be driven to receive injected carriers for adjusting its potential during operation of the MOSFET. In a particular case, the MOSFET may comprise another region of semiconductor material in contiguous relationship with a drain/source region of the MOSFET and on a side thereof opposite to the body region. This additional region may be formed with a conductivity of type opposite the drain/source, and may establish an effective bipolar device per the body, the drain/source and the additional region. The geometries and doping thereof may be designed to establish a transport gain of magnitude sufficient to assist the injection of carriers into the floating body region, yet small enough to guard against inter-latching with the MOSFET.
    Type: Grant
    Filed: September 16, 2006
    Date of Patent: February 10, 2009
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Zachary K. Lee, Farid Nemati, Scott Robins
  • Patent number: 7488626
    Abstract: In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: February 10, 2009
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Kevin J. Yang, Farid Nemati, Scott Robins, James D. Plummer, Hyun-Jin Cho
  • Patent number: 7374974
    Abstract: A thyristor-based semiconductor device includes a thyristor body that has at least one region in the substrate and a thyristor control port in a trenched region of the device substrate. According to an example embodiment of the present invention, the trench is at least partially filled with a dielectric material and a control port adapted to capacitively couple to the at least one thyristor body region in the substrate. In a more specific implementation, the dielectric material includes deposited dielectric material that is adapted to exhibit resistance to voltage-induced stress that thermally-grown dielectric materials generally exhibit. In another implementation, the dielectric material includes thermally-grown dielectric material, and when used in connection with highly-doped material in the trench, grows faster on the highly-doped material than on a sidewall of the trench that faces the at least on thyristor body region in the substrate.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: May 20, 2008
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Andrew Horch, Scott Robins
  • Patent number: 7320895
    Abstract: Switching operations, such as those used in memory devices, are enhanced using a thyristor-based semiconductor device adapted to switch between a blocking state and a conducting state. According to an example embodiment of the present invention, a thyristor-based semiconductor device includes a thyristor having first and second base regions coupled between first and second emitter regions, respectively. A first control port capacitively couples a first signal to the first base region, and a second control port capacitively couples a second signal to the second base region. Each of the first and second signals have a charge that is opposite in polarity, and the opposite polarity signals effect the switching of the thyristor at a lower power, relative to the power that would be required to switch the thyristor having only one control port.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: January 22, 2008
    Assignee: T-Ram Semiconductor, Inc.
    Inventors: Andrew Horch, Scott Robins, Farid Nemati
  • Patent number: 7245525
    Abstract: In a thyristor based memory cell, one end of a reversed-biased diode is connected to the cathode of the thyristor. During standby, the second end of the diode is biased at a voltage that is higher than that at the cathode of the thyristor. During restore operation, the second end is pulled down to zero or even a negative value. If the cell is storing a “1,” the voltage at the thyristor cathode can be approximately 0.6 volt at the time of the pull down. The large forward-bias across the diode pulls down the thryistor cathode. This causes the thyristor to be restored. If the cell is storing a “0,” the voltage at the thyristor cathode can be approximately zero volt. The small or zero forward-bias across the diode is unable to disturb the “0” state. As a result, the memory cell is restored to its original state.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: July 17, 2007
    Assignee: T-Ram Semiconductor, Inc.
    Inventors: Zachary K. Lee, Farid Nemati, Scott Robins