Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

Abstract: In one embodiment, a predefined behavior of a virtual machine monitor (VMM) with respect to one or more virtual machines (VMs) is identified, and processor-managed resources associated with the one or more VMs are utilized based on the predefined behavior of the VMM.

Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.

Abstract: A method for forming planar-waveguide Bragg grating in a curved waveguide comprises: forming a long chirped planar-waveguide Bragg grating in an Archimedes' spiral such that a long length of the waveguide can fit in a small chip area where the grating is formed in the curved waveguide; using periodic width modulation to form the planar-waveguide Bragg grating on the curved waveguide, and where the formation of the periodic width modulation occurs during the etching of the waveguide core; using rectangular width modulation to create Bragg gratings with a higher order than 1st order to allow a larger grating period and larger modulation depth, using waveguide width tapering while keeping the width modulation period constant to introduce chirp to the planar-waveguide Bragg grating where the index of refraction is a function of waveguide width, by applying a specific width tapering to create a desired arbitrary chirp profile.

Abstract: In one embodiment, a predefined behavior of a virtual machine monitor (VMM) with respect to one or more virtual machines (VMs) is identified, and processor-managed resources associated with the one or more VMs are utilized based on the predefined behavior of the VMM.

Abstract: In one embodiment, a predefined behavior of a virtual machine monitor (VMM) with respect to one or more virtual machines (VMs) is identified, and processor-managed resources associated with the one or more VMs are utilized based on the predefined behavior of the VMM.

Abstract: In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.

Abstract: A system and method include forming an optical cavity by positioning a photonic crystal a predetermined distance from a substrate, and creating, within the cavity, a standing wave having a substantially flat wavefront. The standing wave may be created by applying an input wave to a first surface of the photonic crystal. The predetermined distance may be such that a peak intensity of the standing wave is proximate to or a calculated distance from the substrate surface. The peak intensity may vary in relation to the substrate surface. The method may include tuning the peak intensity location within the cavity by shifting the wavelength of the input wave or altering the characteristics of the photonic crystal by an external field. A second photonic crystal may be used on the other side of the substrate to replace the reflecting properties of the substrate, allowing for further smoothing of the wavefront.

Abstract: An optical-powered device includes a flexible substrate, a photonic bandgap layer coupled thereto, a waveguide contained within the photonic bandgap layer, and a dendrimer region contained within the waveguide. The dendrimer region may comprise more than one dendrimers. The dendrimer region emission band is within the photonic bandgap of the photonic bandgap layer. Multiple photonic bandgap layers may be included, with one or more waveguides therein. Each waveguide may have a dendrimer region therein. Electronic circuitry may be contained within a portion of the photonic bandgap layer. A light-modulating layer may be directly coupled to the photonic bandgap layer. A portion of the photonic bandgap layer may have a sensing material embedded therein. A cover layer having one or more windows may be coupled to the photonic bandgap layer. Another layer, such as a buffer layer, may be disposed between the substrate layer and the photonic bandgap layer.

Abstract: In one embodiment, a predefined behavior of a virtual machine monitor (VMM) with respect to one or more virtual machines (VMs) is identified, and processor-managed resources associated with the one or more VMs are utilized based on the predefined behavior of the VMM.

Abstract: In one embodiment, a predefined behavior of a virtual machine monitor (VMM) with respect to one or more virtual machines (VMs) is identified, and processor-managed resources associated with the one or more VMs are utilized based on the predefined behavior of the VMM.

Abstract: A photonic processor having a high spectral resolution which separates an input optic signal into numerous channels and a method of constructing same are provided. The photonic processor includes an optical delay line spiral having dips to compensate for path length differences between the various paths such that each path is an integer multiple of a fixed path length. Straight segments are included in the spiral design to offset the dips in the spiral such that they do not overlap. A number of waveguide taps are included that may launch the channelized light signals into a photonic lens.

Abstract: A Metal Nanoparticle Photonic Bandgap Device in SOI Method (NC#098884). The method includes providing a substrate having a semiconductor layer over an insulator layer, operatively coupling the substrate to a photonic bandgap structure having at least one period, wherein the photonic bandgap structure is adapted to receive and output light along a predetermined path, and operatively coupling the photonic bandgap structure and the substrate to a metal nanoparticle structure comprising at least three metal nanoparticles having spherical shapes of different radii, wherein the at least three metal nanoparticles are adapted to receive and amplify light rays and output amplified light.

Abstract: A technique for coupling electromagnetic energy into an aperture smaller than the wavelength of the electromagnetic energy desired to be coupled is disclosed.

Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed byte data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed byte data and a second packed byte data. The processor performs operations on data elements in said first packed byte data and said second packed byte data to generate a third packed data in response to receiving an instruction. A plurality of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed byte data.