Abstract: Disclosed are a method, apparatus, and computer program product to implement routing for double patterning lithography. A three-phase routing scheme is employed, comprising a global router, a C-router, and a detail router. The C-router provides double patterning color seeding for routing tracks in the electronic design. The detail router employs space-tiles to perform double-patterning based routing for wires in the electronic design.

Abstract: Disclosed are a method, apparatus, and computer program product to implement routing for double patterning lithography. A three-phase routing scheme is employed, comprising a global router, a C-router, and a detail router. The C-router provides double patterning color seeding for shapes on routing tracks in the electronic design. The detail router employs space-tiles to perform double-patterning based routing for wires in the electronic design.

Abstract: Disclosed are a method, apparatus, and computer program product to implement routing for double patterning lithography using colored space tiles. A three-phase routing scheme is employed, comprising a global router, a C-router, and a detail router. The C-router provides double patterning color seeding for routing tracks in the electronic design. The detail router employs space-tiles to perform double-patterning based routing for wires in the electronic design. Colored space tiles may be utilized to perform the detail routing.

Abstract: Disclosed is an improved method, system, and mechanism for using and constructing a minimum spanning tree. In one approach, each iteration of the process for constructing a minimum spanning tree calculates at most two additional point-pairs for nearest neighbors of points previously added to the tree. These additional point-pairs are appended to a list of point pairs, and the point-pair having the shortest distance is selected and added to the minimum spanning tree. Any metric can be employed to determine nearest neighbors, including Euclidean or Manhattan metrics. An advantage is that not all point-pairs need to be examined, greatly increasing speed and efficiency. Since every point-pair does not have to be examined, a preprocessing step is not required to reduce the number of point-pairs being considered. The resultant minimum spanning tree can be used to facilitate the routing process for an integrated circuit.

Abstract: Various embodiments of the invention comprise methods and systems for determining when or whether to use hard rules or preferred rules during global routing of an electronic design. In some embodiments, the entire routable space is first routed with hard rules during global routing while ensuring the design may be embedded. The design is then analyzed with preferred rules where the overcongested areas are marked as “use hard rule” and areas not overcongested are marked as “use preferred rule.” The methods or the systems thus ensure that the design remains routable throughout the process while improving timing, manufacturability, or yield by reserving routing space for the preferred rules.

Abstract: Disclosed is an improved method, system, and mechanism for using and constructing a minimum spanning tree. In one approach, each iteration of the process for constructing a minimum spanning tree calculates at most two additional point-pairs for nearest neighbors of points previously added to the tree. These additional point-pairs are appended to a list of point pairs, and the point-pair having the shortest distance is selected and added to the minimum spanning tree. Any metric can be employed to determine nearest neighbors, including Euclidean or Manhattan metrics. An advantage is that not all point-pairs need to be examined, greatly increasing speed and efficiency. Since every point-pair does not have to be examined, a preprocessing step is not required to reduce the number of point-pairs being considered. The resultant minimum spanning tree can be used to facilitate the routing process for an integrated circuit.

Abstract: Disclosed are improved methods and mechanisms for congestion and maximum flow analysis for routing an integrated circuit design. In one approach, maximum flow analysis is performed by tessellating a portion of a layout to form space tiles, which are used to interpret a flow graph. The flow graph comprises a set of vertices and edges. The capacity of edges in the flow graph is used to identify the maximum flow for that portion of the layout. In another approach, an edge walk is performed against a set of space tiles, in which a nearest neighbor determination is determined for each edge to perform maximum flow analysis.

Abstract: A method of analyzing a design of an electronic circuit uses slices. The method includes generating one or more slices, each slice comprising a contiguous region of the design, and generating an set comprising one or more bins for each slice. A search for an object may be performed by determining a search area, and identifying slices containing at least a portion of the search area. For each identified slice, each object within the search area is associated with one of the bins of the set for the slice.

Abstract: A method of analyzing a design of an electronic circuit includes tessellating the design into a grid of rectangles, selecting at least one rectangle as a first level parent rectangle, and generating a plurality of second level child rectangles based on the first level parent rectangle.

Abstract: Disclosed are improved methods and mechanisms for congestion and maximum flow analysis for routing an integrated circuit design. In one approach, maximum flow analysis is performed by tessellating a portion of a layout to form space tiles, which are used to interpret a flow graph. The flow graph comprises a set of vertices and edges. The capacity of edges in the flow graph is used to identify the maximum flow for that portion of the layout. In another approach, an edge walk is performed against a set of space tiles, in which a nearest neighbor determination is determined for each edge to perform maximum flow analysis.

Abstract: A method of analyzing a design of an electronic circuit may include selecting a query object in a collection of sets of intervals for the design, where each set of intervals along a first common axis, the collection of sets along a second common axis. Candidate objects within the collection that are candidates to be closest to the query object may be identified. A nearest neighbor object is selected from the candidate objects, the nearest neighbor object having shortest distance to the query object.

Abstract: The present invention features a Bacillus anthracis lethal factor substrate. The substrate can be used for example to measure lethal factor activity. Preferred substrates contain one or mare detectable labels and have a sufficiently high turnover rate for applications in a high throughput screen.

Abstract: The present invention features a Bacillus anthracis lethal factor substrate and assays employing the substrate to measure lethal factor activity and to screen for compounds affecting lethal factor activity. Preferred substrates contain one or more detectable labels and have a sufficiently high turnover rate to be suitable for use in a high throughput screen.