Patents by Inventor Scott Stoller

Scott Stoller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11601442
    Abstract: A system associated with detecting a cyber-attack and reconstructing events associated with a cyber-attack campaign, is disclosed. The system performs various operations that include receiving an audit data stream associated with cyber events. The system identifies trustworthiness values in a portion of data associated with the cyber events and assigns provenance tags to the portion of the data based on the identified trustworthiness values. An initial visual representation is generated based on the assigned provenance tags to the portion of the data. The initial visual representation is condensed based on a backward traversal of the initial visual representation in identifying a shortest path from a suspect node to an entry point node. A scenario visual representation is generated that specifies nodes most relevant to the cyber events associated with the cyber-attack based on the identified shortest path. A corresponding method and computer-readable medium are also disclosed.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: March 7, 2023
    Assignees: THE RESEARCH FOUNDATION FOR THE STATE UNIVERSITY OF NEW YORK, THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS
    Inventors: Ramasubramanian Sekar, Junao Wang, Md Nahid Hossain, Sadegh M. Milajerdi, Birhanu Eshete, Rigel Gjomemo, V. N. Venkatakrishnan, Scott Stoller
  • Patent number: 10755793
    Abstract: NAND memory devices are described that utilize higher read-margin cell types to provide a more granular read disturb indicator without utilizing dummy cells. For example, a NAND architecture may have some cells that are configured as SLC or MLC cells. SLC or MLC cells have more read disturb margin—that is these cells can withstand more read disturb current leakage into the cell before a bit error occurs than TLC or QLC cells. These higher margin cells may serve as the read disturb indicator for a group of cells that have a comparatively lower read disturb margin. Since there are more pages of these higher margin cells than there are pages of dummy cells, these indicators may serve a smaller group of pages than the dummy pages. This reduces the time needed to complete a read disturb scan as fewer pages need to be scanned.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: August 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Harish Singidi, Scott Stoller, Jung Sheng Hoei, Ashutosh Malshe, Gianni Stephen Alsasua, Kishore Kumar Muchherla
  • Publication number: 20200059481
    Abstract: A system associated with detecting a cyber-attack and reconstructing events associated with a cyber-attack campaign, is disclosed. The system performs various operations that include receiving an audit data stream associated with cyber events. The system identifies trustworthiness values in a portion of data associated with the cyber events and assigns provenance tags to the portion of the data based on the identified trustworthiness values. An initial visual representation is generated based on the assigned provenance tags to the portion of the data. The initial visual representation is condensed based on a backward traversal of the initial visual representation in identifying a shortest path from a suspect node to an entry point node. A scenario visual representation is generated that specifies nodes most relevant to the cyber events associated with the cyber-attack based on the identified shortest path. A corresponding method and computer-readable medium are also disclosed.
    Type: Application
    Filed: August 19, 2019
    Publication date: February 20, 2020
    Inventors: Ramasubramanian Sekar, Junao Wang, Md Nahid Hossain, Sadegh M. Milajerdi, Birhanu Eshete, Rigel Gjomemo, V.N. Venkatakrishnan, Scott Stoller
  • Publication number: 20190130983
    Abstract: NAND memory devices, are described that utilize higher read-margin cell types to provide a more granular read disturb indicator without utilizing dummy cells. For example, a NAND architecture may have some cells that are configured as SLC or MLC cells. SLC or MLC cells have more read disturb margin—that is these cells can withstand more read disturb current leakage into the cell before a bit error occurs than TLC or QLC cells. These higher margin cells may serve as the read disturb indicator for a group of cells that have a comparatively lower read disturb margin. Since there are more pages of these higher margin cells than there are pages of dummy cells, these indicators may serve a smaller group of pages than the dummy pages. This reduces the time needed to complete a read disturb scan as fewer pages need to be scanned.
    Type: Application
    Filed: October 31, 2017
    Publication date: May 2, 2019
    Inventors: Harish Singidi, Scott Stoller, Jung Sheng Hoei, Ashutosh Malshe, Gianni Stephen Alsasua, Kishore Kumar Muchherla