Abstract: An apparatus can include a touch-up component. The touch-up component can detect that at least one memory cell of a page of memory cells has lost a portion of a charge. The touch-up component can set touch-up parameters for the page of memory cells. The touch-up component can cause a transfer of data from the page of memory cells to a cache. The touch-up component can reprogram the at least one memory cell using the set touch-up parameters.

Abstract: Exemplary methods, apparatuses, and systems including memory self-recovery management to correct failures due to soft-error rate events. The self-recovery manager detects a failure of a memory device. The self-recovery manager retrieves a set of register values from the memory device. The self-recovery manager stores the set of register values from the memory device. The self-recovery manager issues a reset command to the memory device, the reset command including generating a re-initialized set of register values. The self-recovery manager compares the set of register values with the re-initialized set of register values. The self-recovery manager triggering a self-recovery attempt using the comparison of the set of register values with the re-initialized set of register values.

Abstract: A system and method for data collection and aggregation using a distributed network of communications enabled sensors connected to another primary network to achieve a secondary out-of-band monitoring perspective, for example, in power grids. The data collection system includes an aggregation and processing server configured to collect data from a variety of sensors adjacent to the monitored network each sensor includes secondary power such that it can continue data transmission even during power grid outages. The data collection system includes a method for secure real-time data ingest, machine learning enabled analysis, risk assessment, and anomaly detection on a broad geographic scale irrespective of isolated network boundaries.

Abstract: Exemplary methods, apparatuses, and systems including memory self-recovery management to correct failures due to soft-error rate events. The self-recovery manager detects a failure of a memory device. The self-recovery manager retrieves a set of register values from the memory device. The self-recovery manager stores the set of register values from the memory device. The self-recovery manager issues a reset command to the memory device, the reset command including generating a re-initialized set of register values. The self-recovery manager compares the set of register values with the re-initialized set of register values. The self-recovery manager triggering a self-recovery attempt using the comparison of the set of register values with the re-initialized set of register values.

Abstract: An apparatus can include a touch-up component. The touch-up component can detect that at least one memory cell of a page of memory cells has lost a portion of a charge. The touch-up component can set touch-up parameters for the page of memory cells. The touch-up component can cause a transfer of data from the page of memory cells to a cache. The touch-up component can reprogram the at least one memory cell using the set touch-up parameters.

Abstract: Memory systems with flexible erase suspend-resume operations are described herein. In one embodiment, a memory device is configured to receive an erase suspend command while a first erase pulse of an erase operation is at a flattop voltage. In response, the memory device suspends the erase operation. The memory device further resumes the erase operation such that a second erase pulse of the erase operation is ramped to the flattop voltage. Absent intervening erase suspend operations, erase operations of the memory device can include a single erase pulse that remains at the flattop voltage for a total duration. A first total duration plus a second total duration the first and second erase pulses, respectively, remain at the flattop voltage remains less than or equal to the total duration the single erase pulse remains at the flattop voltage.

Abstract: A determination is made that a memory device of a memory sub-system is to be transitioned to a sleep mode. A command is initiated to cause a standby circuit associated with the memory device to enter into a low power mode while a power supply of the memory sub-system is maintained in a powered state. In the low power mode, a reference voltage is supplied to a voltage regulator of the standby circuit to supply a standby current level to the memory device during the sleep mode.

Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.

Abstract: A method is described that includes determining a number of program and erase cycles associated with a block of pages of a memory device and determining a preprogram voltage based on the number of program and erase cycles to apply to the block of pages prior to an erase operation. The method further includes applying the preprogram voltage to the block of pages and performing an erase operation on the block of pages following application of the preprogram voltage to the block of pages.

Abstract: Read calibration by sector of memory can include reading a page of memory, having more than one sector, with a read level, such as a default read level. In response to an error, such as an uncorrectable error correction code read result, the respective read level can be calibrated for each sector to yield a respective calibrated read level per sector. The page of memory can be read with the respective calibrated read level per sector. The calibrated read levels can be stored.

Abstract: A processing device in a memory system detects a data loss occurrence in a block of a memory component. The processing device further designates the block as a quarantined block, performs a stress test on the block, and depending on whether the stress test on the block satisfies a testing criterion, either designates the block as usable by the memory component or retires the block of the memory component.

Abstract: A method includes determining, for a set of memory cells of a word line group, a parameter corresponding to a quality of the set of memory cells of the word line group and determining, for the set of memory cells, a range of voltage offset values corresponding to the parameter. The method can further include determining a voltage offset to be applied to the set of memory cells of the word line group based on the parameter or the range of voltage offset values, or both and applying a signal corresponding to the determined voltage offset to the set of memory cells of the word line group.

Abstract: A system associated with detecting a cyber-attack and reconstructing events associated with a cyber-attack campaign, is disclosed. The system performs various operations that include receiving an audit data stream associated with cyber events. The system identifies trustworthiness values in a portion of data associated with the cyber events and assigns provenance tags to the portion of the data based on the identified trustworthiness values. An initial visual representation is generated based on the assigned provenance tags to the portion of the data. The initial visual representation is condensed based on a backward traversal of the initial visual representation in identifying a shortest path from a suspect node to an entry point node. A scenario visual representation is generated that specifies nodes most relevant to the cyber events associated with the cyber-attack based on the identified shortest path. A corresponding method and computer-readable medium are also disclosed.

Abstract: Described are systems and methods for providing power loss immunity in memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: causing a programming pulse to be applied to to one or more wordlines of the memory array; responsive to determining that a threshold voltage of one or more memory cells of the memory array has reached a pre-program verify level, causing a first bias voltage level to be applied to a first subset of bitlines of the memory array and causing a second bias voltage level to be applied to a second subset of bitlines of the memory array.

Abstract: A method is described that includes determining a number of program and erase cycles associated with a block of pages of a memory device and determining a preprogram voltage based on the number of program and erase cycles to apply to the block of pages prior to an erase operation. The method further includes applying the preprogram voltage to the block of pages and performing an erase operation on the block of pages following application of the preprogram voltage to the block of pages.

Abstract: Described are systems and methods for providing power loss immunity in memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: causing a programming pulse to be applied to to one or more wordlines of the memory array; responsive to determining that a threshold voltage of one or more memory cells of the memory array has reached a pre-program verify level, causing a first bias voltage level to be applied to a first subset of bitlines of the memory array and causing a second bias voltage level to be applied to a second subset of bitlines of the memory array.

Abstract: A method and system for temperature-dependent operations in a memory device are described. Temperature measurements of a memory device are recorded. A determination that a temperature measurement of the memory device satisfies a threshold temperature value is performed. In response to the determination, execution of a background operation in the memory device is delayed, and host system operation(s) continue to be executed in the memory device while execution of the background operation is delayed.

Abstract: A method is described that includes determining a number of program and erase cycles associated with a block of pages of a memory device and determining a preprogram voltage based on the number of program and erase cycles to apply to the block of pages prior to an erase operation. The method further includes applying the preprogram voltage to the block of pages and performing an erase operation on the block of pages following application of the preprogram voltage to the block of pages.

Abstract: A method and system for temperature-dependent operations in a memory device are described. Temperature measurements of a memory device are recorded. A determination that a temperature measurement of the memory device satisfies a threshold temperature value is performed. In response to the determination, execution of a background operation in the memory device is delayed, and host system operation(s) continue to be executed in the memory device while execution of the background operation is delayed.

Abstract: A method is described that includes performing a first erase operation on a set of memory cells of a memory device using an erase voltage, which is set to a first voltage value and adjusting the erase voltage to a second voltage value based on feedback from performance of at least the first erase operation. The method further includes performing a second erase operation on the set of memory cells using the erase voltage, which is set to the second voltage value. In this configuration, the erase voltage set to the second voltage value is an initial voltage applied to the set of memory cells to perform erase operations such that each subsequent erase operation on the set of memory cells following the first erase operation uses an erase voltage that is equal to or greater than the second voltage value when erasing the first set of memory cells.