Abstract: A method includes performing a validation process on a firmware feature description file indicating a set of firmware features in an integrated circuit package, and communicating a result of the validation process to firmware feature enablement logic residing in the integrated circuit package.

Abstract: A method includes, in response to a request to enable a set of firmware features in a processing device, performing a validation process based on a key certificate associating a first entity identifier with a firmware feature description file indicating the set of firmware features, and in response to a violation detected during the validation process, enabling a countermeasure in the processing device.

Abstract: A computing system and bus bridge in which the bus bridge includes a buffer pool wherein the storage buffers contained in the buffer pool may be allocated as post buffers or fetch buffers in response to appropriate requests from the bus bridge. In the preferred embodiment, the bus bridge includes a buffer pool control unit adapted to temporarily allocate any of the plurality of storage buffers as either a post buffer or a fetch buffer depending upon the system requirements. Broadly speaking, the present invention contemplates a computing system including a first component connected to a first bus, a second component connected to a second bus, and a bus bridge connected to a first and second busses. The bus bridge includes a buffer pool comprised of a plurality of storage buffers and a buffer pool control unit that is capable of temporarily allocating at least one of the storage buffers as either a post buffer or a fetch buffer in response to system requirement.

Abstract: A cache memory system comprising a first bus for connecting to a bus master and a second bus for connecting to a system memory. The system memory comprises a plurality of cacheable memory locations. A bus bridge provides an interface between the first bus and the second bus. A cache memory controller for caching data stored in the cacheable memory locations is connected to the system memory. The cache memory controller includes a snoop control circuit directly coupled to the first bus for snooping bus transactions upon the first bus and further coupled to the second bus for snooping bus transactions on said second bus.

Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes byte slicing logic coupled to one or more of the expansion bus and/or the multimedia bus which operates to allow different data streams to use different byte channels simultaneously. Thus the byte sliced multimedia bus allows different peripherals to share the bus simultaneously. The byte slicing logic thus may assign one data stream to a subset of the total byte lanes on the multimedia bus, and fill the unused byte lanes with another data stream. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.

Abstract: A computer system comprising an improved DMA controller for performing DMA transfers between a peripheral device and system memory and receiving and servicing interrupts generated by the peripheral device. The system comprises one or more buses for transferring data. A CPU, system memory and a plurality of peripheral devices are interconnected by the buses. Each of the peripheral devices comprises one or more peripheral interrupt request outputs. The system further comprises a programmable DMA controller coupled to the bus which receives the peripheral interrupt request outputs. The DMA controller is configured to perform a DMA transfer on the one or more buses between two or more devices, including the system memory and the plurality of peripheral devices. The CPU programs the DMA controller to start the DMA transfer in response to one of the plurality of peripheral devices generating an interrupt request on its interrupt request output or to start the DMA transfer immediately.

Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes byte slicing logic coupled to one or more of the expansion bus and/or the multimedia bus which operates to allow different data streams to use different byte channels simultaneously. Thus the byte sliced multimedia bus allows different peripherals to share the bus simultaneously. The byte slicing logic thus may assign one data stream to a subset of the total byte lanes on the multimedia bus, and fill the unused byte lanes with another data stream. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.

Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes a dedicated or centralized I/O processor coupled to one or more of the expansion bus and/or the multimedia bus which operates to direct or pull stream information through the system. The centralized I/O processor comprises a memory for storing data rate, data periodicity, data source, and data destination information for the multimedia devices. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.

Abstract: A method for performing data transfers in a computer system comprising an improved DMA controller (DMAC) for performing DMA transfers between a peripheral device and system memory and receiving and servicing interrupts generated by the peripheral device. The system comprises a CPU, system memory, the DMA controller and a plurality of peripheral devices interconnected by buses. The CPU programs the peripheral, such as a disk drive, to retrieve or store data. When the peripheral has retrieved the data or is ready to receive the data the peripheral generates an interrupt. The CPU programs the DMAC to perform DMA transfers between the peripheral and the system memory and to selectively decouple the interrupt request from the peripheral to the CPU so that the DMAC can service the interrupt from the peripheral rather than the CPU. The decoupling is selectively performed so that, in the case of a write to the peripheral, the DMAC can receive the interrupt from the peripheral and perform the data transfer.

Abstract: A dockable computer system includes a portable computer (notebook or laptop) and a docking station (base unit). The portable computer and docking station both include a communication system so that messages can be communicated when the docking station is in an undocked state preparatory to a docked state. The communication system is preferably an infrared communication system. A communication protocol is also provided for generating an advance notice signal to warn of an impending dock. The communication protocol includes a CONNECT message, a CONNECT DETECTED message, and a CONFIRM message. Preferably, the CONNECT message is sent at a non-standard AT/PC baud rate. The communication system allows the dockable computer system to advantageously generate an advance notice signal of an impending dock and to transfer parameters necessary for the employment of sophisticated protective measures which protect the active buses of the portable computer and docking station during a docking event.

Abstract: A computer system includes a bus arbiter for providing immediate access to a bus in response to an external requirement or event. In a dockable computer system capable of hot docking or warm docking, the bus arbiter grants exclusive, non-preemptive access to the buses to the docking agent which is capable of quieting (rendering inactive) the bus of the portable computer and docking station in response to a notice signal. The notice signal is indicative of a change of states from the undocked state to the docked state or from the docked state to the undocked state. The notice signal may be provided from software, a user-actuated switch, or an infrared signal. In an audio-capable computer, the bus arbiter provides exclusive non-preemptive access to the digital signal processing peripheral device so that audio glitches are avoided.

Abstract: In a dockable computer system capable of hot docking or warm docking, a docking safe circuit drives the bus of the portable computer and docking station to a docking safe state in response to a DOCK signal. The DOCK signal may be a notice signal indicative of a change of state from the undocked state to the docked state or from the docked state to the undocked state. The notice signal may be provided from software, a user-actuated switch or an infrared signal. Preferably, the docking safe state or dockable state is a state in which: the ground conductors of the buses are referenced to a common ground potential; the buses are "quiet" or non-transitioning; the bidirectional terminals on the bus of the portable computer are set to an output state; the bidirectional terminals of the bus of the docking station are set to an input state; and the signaling levels of the buses have the same voltage potential. Preferably, the present invention is implemented on a peripheral component interconnect (PCI) bus.

Abstract: A dockable computer system is capable of performing hot docking or warm docking. Hot docking refers to an ability to dock when the portable computer or docking station are running at full power. Warm docking refers to an ability to dock when the portable computer and docking station are running in a reduced power state. The dockable computer system employs a docking agent which is capable of quieting (rendering inactive) the buses of the portable computer and docking station in response to a notice signal. The notice signal is indicative of a change of states from the undocked state to the docked state or from the docked state to the undocked state. The notice signal can be provided from software, a user-actuated switch, or an infrared signal. The docking agent preferably quiets the system bus by idling the system bus or asserting bus ownership or bus mastership over the system bus. The docking agent is able to assert bus ownership or bus mastership over the system bus.